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Dive into the research topics where M. Wurzer is active.

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Featured researches published by M. Wurzer.


bipolar/bicmos circuits and technology meeting | 2004

SiGe bipolar technology for automotive radar applications

J. Bock; Herbert Schäfer; K. Aufinger; R. Stengl; Sabine Boguth; R. Schreiter; M. Rest; Herbert Knapp; M. Wurzer; Werner Perndl; T. Bottner; T.F. Meister

A SiGe bipolar technology for automotive radar applications around 77 GHz has been developed. A cut-off frequency of 200 GHz, a maximum oscillation frequency of 275 GHz, and a gate delay of 3.5 ps have been obtained. First key building blocks for 77 GHz systems like VCOs and mixers have been realized with this technology.


international electron devices meeting | 2002

Sub 5 ps SiGe bipolar technology

J. Bock; Herbert Schäfer; Herbert Knapp; D. Zoschg; Klaus Aufinger; M. Wurzer; Sabine Boguth; M. Rest; R. Schreiter; R. Stengl; T.F. Meister

A SiGe bipolar technology for mixed digital and analog RF applications is presented. Balanced device performance is achieved with a transit frequency f/sub T/ of 155 GHz at a collector emitter breakdown voltage BV/sub CEO/ of 1.9 V, a maximum oscillation frequency f/sub max/ of 167 GHz, and 4.7 ps ring oscillator gate delay. With a 99 GHz dynamic frequency divider and a 19 GHz LNA with 2.2 dB noise figure state-of-the-art results for high-speed digital and analog applications are demonstrated.


international electron devices meeting | 2004

3.3 ps SiGe bipolar technology

J. Bock; Herbert Schäfer; Herbert Knapp; Klaus Aufinger; M. Wurzer; Sabine Boguth; T. Bottner; R. Stengl; W. Perndl; T.F. Meister

A SiGe bipolar technology with a transit frequency of 225 GHz and a maximum oscillation frequency of 300 GHz is described. With a ring oscillator gate delay of 3.3 ps and a static frequency divider operating up to 102 GHz input frequency state-of-the-art circuit performance is achieved.


international electron devices meeting | 2001

High-speed SiGe:C bipolar technology

J. Bock; Herbert Schäfer; Herbert Knapp; D. Zoschg; Klaus Aufinger; M. Wurzer; Sabine Boguth; R. Stengl; R. Schreiter; Thomas Meister

A SiGe:C bipolar technology with a narrow base integrated into a double-polysilicon self-aligned transistor has been developed. A transit frequency of 106 GHz at a collector emitter breakdown voltage of 2.3 V, a maximum oscillation frequency of 145 GHz, and 6.5 ps gate delay demonstrate balanced transistor performance. State-of-the-art results for high-speed digital, analog, and low-power circuits are achieved.


international electron devices meeting | 2000

SiGe bipolar technology for mixed digital and analogue RF applications

J. Bbck; Thomas Meister; Herbert Knapp; D. Zoschg; Herbert Schäfer; Klaus Aufinger; M. Wurzer; Sabine Boguth; M. Franosch; R. Stengl; R. Schreiter; M. Rest; Ludwig Treitinger

A SiGe bipolar technology with a low-resistivity base integrated into a double-polysilicon self-aligned transistor has been developed. A transit frequency of 85 GHz, a maximum oscillation frequency of 128 GHz, 6.8 ps gate delay, and a minimum noise figure of 1.2 dB at 10 GHz demonstrate balanced transistor performance. With an 88 GHz dynamic frequency divider and a 12 GHz low noise amplifier with 1.9 dB noise figure, state-of-the-art results for digital as well as analogue applications are achieved.


international microwave symposium | 2002

40 GHz monolithic integrated mixer in SiGe bipolar technology

S. Hackl; Josef Böck; M. Wurzer; Arpad L. Scholtz

Future broadband wireless services will use carrier frequencies in the range of 10 GHz to about 42 GHz. This raises the demand for low-cost components of key RF building blocks like LNAs, mixers, and oscillators for frequencies up to 42 GHz. This work describes an active mixer in a pre-production 0.4 /spl mu/m SiGe bipolar technology with bandwidth in the range mentioned above. A gain of 25 dB and double-sideband noise figure of 15 dB is achieved at 40 GHz.


international solid-state circuits conference | 2002

25 GHz static frequency divider and 25 Gb/s multiplexer in 0.12 /spl mu/m CMOS

Herbert Knapp; Hans-Dieter Wohlmuth; M. Wurzer; M. Rest

A static 2:1 frequency divider operating up to 25.4 GHz at 41 mA and a 25 Gb/s 2:1 multiplexer at 29 mA implemented in current-mode logic have differential 50 /spl Omega/ inputs and outputs. They are fabricated in a 0.12 /spl mu/m CMOS process and operate from a 1.5 V supply.


international solid-state circuits conference | 2000

A 79 GHz dynamic frequency divider in SiGe bipolar technology

Herbert Knapp; Thomas Meister; M. Wurzer; D. Zoschg; Klaus Aufinger; L. Treitlinger

Conventional static frequency dividers use master-slave flipflops to achieve frequency division. They allow broadband operation down to DC as long as the slew rate of the input signal is high enough. Their upper frequency, however, is Limited by the gate delay /spl tau//sub D/ to a value of approximately 1/(2 /spl tau//sub D/). Significantly higher operating frequencies can be achieved by dynamic frequency dividers. The limited bandwidth of dynamic dividers is a drawback but poses no problem in many applications which require divider operation only in a specific frequency range. Dynamic dividers manufactured in III-V-technologies and, recently, in SiGe technology achieve maximum operating frequencies of 60 GHz to 75 GHz. However, most of these circuits operate over relatively narrow bandwidths of less than one octave. This regenerative frequency divider exploits the high-speed potential of SiGe technologies to combine high maximum frequency with operation over wide frequency range.


international solid-state circuits conference | 2002

A 45 GHz SiGe active frequency multiplier

S. Hackl; Josef Böck; G. Ritzberger; M. Wurzer; Herbert Knapp; L. Treitinger; Arpad L. Scholtz

A frequency quadrupler for frequencies up to 45 GHz uses a pre-production 0.4 /spl mu/m SiGe bipolar technology. Gain is achieved at -15 dBm input power between 24 and 45 GHz with maximum of 7.3 dB at 44 GHz. The circuit draws 84 mA from a single 5 V supply.


international solid-state circuits conference | 2003

40Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120nm CMOS

Daniel Kehrer; Hans-Dieter Wohlmuth; Herbert Knapp; M. Wurzer; Arpad L. Scholtz

A 40Gb/s 2:1 multiplexer in 120nm 1.2V CMOS uses inductive peaking and output series inductor. A companion 1:2 demultiplexer is also described.

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Arpad L. Scholtz

Vienna University of Technology

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