Maarten Leys

Selective Area Growth of InP in Shallow-Trench-Isolated Structures on Off-Axis Si(001) Substrates

In this paper, we report a comprehensive investigation of InP selective growth in shallow trench isolation (STI) structures on Si(001) substrates 6° off-cut toward (111). Extended defect-free InP layers were obtained in the top region of 100 nm wide trenches. A thin Ge epitaxial layer was used as an intermediate buffer layer between the Si substrate and the InP layer. A Ge buffer was used to reduce the thermal budget for surface clean and to promote double-step formation on the surfaces. Baking the Ge surface in an As ambient improved the InP surface morphology and crystalline quality. InP showed highly selective growth in trenches without nucleation on SiO 2 . However, strong loading effects were observed at all growth pressures, which induced variation in local growth rates. We found trench orientation dependence of facet and stacking fault formation. More stacking faults and nanotwins originated from the STI sidewalls in [110] trenches. High quality InP layers were obtained in the top of the trenches along [110]. The stacking faults generated by the dissociation of threading dislocations are trapped at the bottom of the trenches with an aspect ratio greater than 2.

Selective epitaxial growth of InP in STI trenches on off-axis Si(001) substrates

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Selective epitaxial growth of III-V semiconductor heterostructures on Si substrates for logic applications

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Selective Epitaxial Growth of GaAs on Ge Substrates with a SiO2 Pattern

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(Invited) Epitaxial Growth of III-Nitrides on Silicon Substrates

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Transmission electron microscopy characterisation of Ti and Al/Ti contacts on GaN and AlGaN/GaN

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices.

Growth, processing and characterization of GaN/AlGaN/SiC vertical n-p diodes

We are reporting on a growth procedure for selective growth of GaAs on Ge substrates by organometallic vapor phase deposition. The precursors used for the growth are Tertiarybutylarsine (TBAs) and Trimethylgallium (TMGa). As a mask material 200 nm thick polycrystalline SiO2 was deposited on a 6° miscut Ge(001) substrate. The patterns available on the mask are various structures with feature sizes ranging from a fraction of a micron to a mm square. The filling factor of the mask, defined by the ratio of open area on the substrate to the area covered by SiO2, is approximately 2⁄3. This means that most of the wafer is covered with SiO2, making loading effects due to enhanced concentration of growth species at the mask openings very apparent. The most critical processing step during the selective growth of GaAs on Ge is the growth of the nucleation layer. This nucleation layer needs to be grown at high pressure in order to maximize the As partial pressure, which avoids formation of anti phase domains during the initial nucleation stages. Unfortunately, at high pressure, the nucleation of GaAs on the SiO2 is largest as well. As a result, during the initial growth steps, a small amount of GaAs is nucleated on the SiO2 area, which should be avoided. By keeping the high pressure nucleation layer as thin as possible and by reducing the pressure in the reactor as fast as possible, this nucleation can be avoided. A detailed study of the growth sequence for this nucleation layer has been undertaken, showing the tradeoff between thin high pressure nucleation layer and presence of anti-phase domains in the final selectively grown GaAs layer. Loading effects due to enhanced growth at the boundaries of the SiO2 layer are studied as well. Characterization of the material was done with X-ray diffraction, defect etching, cross-section scanning electron microscopy, photoluminescence spectroscopy and Nomarski microscopy. The final results show that the growth of high quality anti phase domain-free GaAs on Ge is possible, with no GaAs nucleation on the SiO2 mask material. A loading effect at the boundaries of the GaAs is still present and can not be eliminated with the present growth precursors. Figure 1: Nomarski microscope picture of a selectively grown GaAs structure on a 6° miscut Ge substrate. The mask material is a 200 nm thick SiO2 film.

Selective Area Growth of InP on On-Axis Si(001) Substrates with Low Antiphase Boundary Formation

Hetero epitaxial structures with strained layers are widely used in electronic and optoelectronic semiconductor devices. Over the last decades the group III-Nitride semiconductor materials have been extensively used for light emitting applications and are nowadays emerging as promising candidates for high power electronic applications. Unlike the “classical” semiconductor materials (based on Si, Ge, GaAs, InP), group III-Nitrides crystallize in the wurtzite structure and thus have a hexagonal lattice. Furthermore, as no native substrates are available for the III-Nitrides, growth is performed on foreign substrates such as sapphire, siliconcarbide or silicon. III-Nitride epi layers grown on silicon substrates offer a lower cost technology compared to other substrates because of the scalability towards larger wafer size and the leveraging on Si technology. However, the large thermal and lattice mismatch between IIINitrides and silicon requires advanced deposition schemes to allow compensating for the huge tensile thermal stresses and to reduce the dislocation density in these materials. In the early nineties, high quality GaN has been first demonstrated on sapphire substrates. The use of low temperature AlN or GaN nucleation layers strongly improved the crystalline quality. A three-dimensional (3D) to two-dimensional (2D) transition was observed during the high temperature GaN growth on top of a low temperature nucleation layer. It was found that better crystalline quality could be achieved if the coalescence process was intentionally delayed using either low V/III ratio or relatively high pressure controlling as such the density and size of nuclei in the nucleation layer. However, the dislocation density in hetero epitaxial GaN layers is still rather large, in the range of 10 /cm. A further reduction of the dislocation density can be obtained by applying epitaxial lateral overgrowth (ELOG) AlN or AlN/SixNy inter layers. In the last decade, GaN-on-Si has received a lot of attention and exciting results have been demonstrated. The large thermal and lattice mismatch between GaN epitaxial layers and Si substrates lead to severe wafer bowing and even cracking of the epitaxial GaN layers, however low temperature AlN interlayers, Al(Ga)N/GaN superlattices and AlGaN inter layers have been applied to compensate the large thermal tensile stress in the GaN layers imposed by the Si substrate in order to prevent the generation of cracks. Many difficulties still remain, notably in obtaining the highest GaN material quality with respect to (extended) defect density and unintentional background impurity levels. Control of these properties is essential to improve device performance. We have shown that it is possible to grow thick semi-insulating GaN layers on Si(111) substrates with symmetric (0002) peak FWHM as low as 600 arcsec and asymmetric (1-102) peaks as narrow as 830 arcsec. This requires growth temperatures of 1130°C or above (see figure 1). SIMS measurements reveal that carbon is the major impurity in our GaN layers but the concentration can be decreased to well below 10cm, when using sufficiently high growth temperature. Low-temperature PL shows that in such layers no defect-related transitions occur. These defectfree GaN layers have a very high resistivity of beyond 10Ωcm and are thus suitable as buffer layers in dispersion free HEMT devices. In samples grown at temperatures below 1100°C, both Blue Luminescence (BL) and Yellow Luminescence (YL) were observed. The BL band can be attributed to the DAP transition involving recombination via CGa–CN. The YL could originate either from carbon complexes Ci–CGa or Ci–CN, as in our samples the dominant unintentionally incorporated impurity is carbon. Alternatively, the YL is due to the VGa–ON complex localized on edge-type dislocations and would then be of similar origin as the YL band in n-type GaN grown on sapphire substrates.

GaN-on-Si for Power Conversion

Transmission electron microscopy has been applied to study Ti and Al/Ti contacts on GaN and AlGaN/GaN as a function of annealing temperature. This has lead to a profound understanding of the role of Al, both in the contact formation on n-GaN and on AlGaN/GaN. Al in the AlGaN decreases the N-extraction by Ti out of the nitride, because of the strong Al-N bond. Al in the metal bilayer also reduces the N-extraction by Ti due to a preferential alloy mixing.

Study of intrinsically carbon-doped AlGaAs layers for tunnel diodes in multi-junction solar cells

Application of SiC substrates instead of the most commonly used sapphire for the heteroepitaxial growth of III-Nitrides offers advantages as better lattice matching, higher thermal conductivity, and electrical conductivity. This namely offers interesting perspectives for the development of vertical III-Nitride devices for switching purposes. For example, an AlGaN/SiC heterojunction could improve the performance of SiC bipolar transistors. In this work, n-type GaN layers have been grown by MOVPE on p-type 4H-SiC substrates using Si doped Al 0.08 Ga 0.92 N or Al 0.3 Ga 0.7 N nucleation layers. They have been characterized with temperature dependent current-voltage ( I-V-T ), capacitance-voltage ( C-V ) techniques and transmission electron microscopy (TEM).