Denis Marcon

Time-dependent degradation of AlGaN/GaN high electron mobility transistors under reverse bias

This paper describes a detailed analysis of the time-dependent degradation kinetics of GaN-based high electron mobility transistors submitted to reverse-bias stress. We show that: (1) exposure to reverse-bias may induce recoverable changes in gate leakage and threshold voltage, due to the accumulation of negative charge within the AlGaN layer, and of positive charge at the AlGaN/GaN interface. (2) Permanent degradation consists in the generation of parasitic leakage paths. Several findings support the hypothesis that permanent degradation is due to a defect percolation process: (2(a)) for sufficiently long stress times, degradation occurs even below the “critical voltage” estimated by step stress experiments; (2(b)) before permanent degradation, gate current becomes noisy, indicating an increase in defect concentration; and (2(c)) time to breakdown strongly depends on the initial defectiveness of the samples.

Low On-Resistance High-Breakdown Normally Off AlN/GaN/AlGaN DHFET on Si Substrate

Ultrathin-barrier normally off AlN/GaN/AlGaN double-heterostructure field-effect transistors using an in situ SiN cap layer have been fabricated on 100-mm Si substrates for the first time. The high 2DEG density in combination with an extremely thin barrier layer leads to enhancement-mode devices with state-of-the-art combination of specific on-resistance that is as low as 1.25 m¿·cm2 and breakdown voltage of 580 V at V GS = 0 V . Despite the 2-¿m gate length used, the transconductance peaks above 300 mS/mm. Furthermore, pulsed measurements show that the devices are dispersion free up to high drain voltage V DS = 50 V. More than 200 devices have been characterized in order to confirm the reproducibility of the results.

Record Breakdown Voltage (2200 V) of GaN DHFETs on Si With 2-

In this letter, we present a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (V_BD) of AlGaN/GaN/AlGaN double heterostructure FETs on a Si (111) substrate with only 2-μm-thick AlGaN buffer. Before local Si removal, V_BD saturates at ~700 V at a gate-drain distance (L_GD) ≥ 8 μm. However, after etching away the substrate locally, we measure a record V_BD of 2200 V for the devices with L_GD = 20 μm. Moreover, from Hall measurements, we conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties.

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In this letter, we present a novel approach to enhance the breakdown voltage (<i>V</i>_BD) for AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs), grown by metal-organic chemical vapor deposition on Si (111) substrates through a silicon-substrate-removal and a layer-transfer process. Before removing the Si substrate, both buffer isolation test structures and DHFET devices showed a saturation of <i>V</i>_BD due to the electrical breakdown through the Si substrate. We observed a <i>V</i>_BD saturation of 500 V for isolation gaps larger than 6 μm . After Si removal, we measured a <i>V</i>_BD enhancement of the AlGaN buffer to 1100 V for buffer isolation structures with an isolation gap of 12 μm. The DHFET devices with a gate-drain (<i>L</i>_GD) distance of 15 μm have a V_BD > 1100 V compared with ~300 V for devices with Si substrate. Moreover, from Hall measurements, we conclude that the substrate-removal and layer-transfer processes have no impact on the 2-D electron gas channel properties.

Buffer Thickness by Local Substrate Removal

This paper presents a comprehensive review of AlGaN/GaN high electron mobility transistor failure physics and reliability, focusing on mechanisms affecting the gate-drain edge, where maximum electric field and peak temperatures are reached. Physical effects at the origin of device degradation (inverse piezoelectric effect, time-dependent trap formation and percolative conductive paths formation, and electrochemical AlGaN and GaN degradation) are discussed on the basis of literature data and unpublished results. Thermally activated mechanisms involving metal-metal and metal-semiconductor interdiffusion at the gate Schottky junction are also discussed.

Silicon Substrate Removal of GaN DHFETs for Enhanced (<1100 V) Breakdown Voltage

In this work, the gate degradation of GaN-based HEMTs is analyzed. We find that the gate degradation does not occur only beyond a critical voltage, but it has a strong voltage accelerated kinetics and a weak temperature dependence. By means of a statistical study we show that the time-to-failure can be fitted best with a Weibull distribution. By using the distribution parameters and a power law model it is possible to perform lifetime extrapolation based on the gate degradation at a defined failure level and temperature for the first time. From this elaboration, the lifetime of a given device geometry can also be extracted. Eventually, the strong bias dependence of the gate degradation reported here implies that this phenomenon should be assessed by means of a voltage-based accelerated investigation as described in this work.

AlGaN/GaN-Based HEMTs Failure Physics and Reliability: Mechanisms Affecting Gate Edge and Schottky Junction

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown, and reverse-bias stress tests, and provides the following, relevant, information: 1) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the on-resistance (RON), and in a slight shift in threshold voltage; 2) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; 3)current transient measurements indicate the existence of one trap level, with activation energy of 1.03 ± 0.09 eV; and 4) we demonstrate that through the improvement of the fabrication process, it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments in off-state. Results indicate that exposure to moderate-high reverse bias (<; 250 V for LGD = 2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse voltages (typically, VDS = 260-265 V, on a device with LGD = 2 μm stressed with VGS = - 8 V) and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e., in a region where the electric field is maximum.

A comprehensive reliability investigation of the voltage-, temperature- and device geometry-dependence of the gate degradation on state-of-the-art GaN-on-Si HEMTs

This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate. The exposure to OFF-state bias induces a significant increase in the ON-resistance (Ron) of the devices. Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) Ron-increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C-140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the Ron-increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length.

Trapping and Reliability Assessment in D-Mode GaN-Based MIS-HEMTs for Power Applications

This paper describes an extensive analysis of the role of off-state and semi-on state bias in inducing the trapping in GaN-based power High Electron Mobility Transistors. The study is based on combined pulsed characterization and on-resistance transient measurements. We demonstrate that—by changing the quiescent bias point from the off-state to the semi-on state—it is possible to separately analyze two relevant trapping mechanisms: (i) the trapping of electrons in the gate-drain access region, activated by the exposure to high drain bias in the off-state; (ii) the trapping of hot-electrons within the AlGaN barrier or the gate insulator, which occurs when the devices are operated in the semi-on state. The dependence of these two mechanisms on the bias conditions and on temperature, and the properties (activation energy and cross section) of the related traps are described in the text.

Kinetics of Buffer-Related RON-Increase in GaN-on-Silicon MIS-HEMTs

In this paper, we review and add additional data and understandings on our findings on the two most common failure modes of GaN-based HEMTs: 1) permanent gate leakage current increase and 2) output current drop. We suggested that they have different origins and one is not necessarily correlated to the other. Yet, they can both concur to the device degradation. First, we demonstrate that the phenomenon of gate leakage current increase has a voltage-accelerated degradation kinetic. Therefore, the identification of the critical voltage for leakage increase is meaningless. We demonstrate that the time-to-breakdown tBD data are Weibull distributed and we prove that they represent intrinsic failures. According to our data, this phenomenon is not related to the inverse piezoelectric effect. Finally, a new degradation model for the gate leakage current increase based on the percolation path theory is proposed. Second, we show that the permanent output current drop is a consequence of the relaxation of AlGaN layer. This occurs by means of formation of crystallographic defects as described by the inverse piezoelectric degradation model. Finally, we show an excellent stability of devices with reduced Al content in the AlGaN barrier, proving the crucial role of strain in the reliability of AlGaN/GaN HEMTs.