Marleen Van Hove

AlGaN/GaN/AlGaN Double Heterostructures Grown on 200 mm Silicon (111) Substrates with High Electron Mobility

In this work, we demonstrate, for the first time, Al0.35GaN/GaN/Al0.25GaN double heterostructure field effect transistors on 200 mm Si(111) substrates. Thick crack-free Al0.25GaN buffer layers are achieved by optimizing Al0.75GaN/Al0.5GaN intermediate layers and AlN nucleation layers. The highest buffer breakdown voltage reaches 1380 V on a sample with a total buffer thickness of 4.6 µm. According to Van der Pauw Hall measurements, the electron mobility is 1766 cm2 V-1 s-1 and the electron density is 1.16×1013 cm-2, which results in a very low sheet resistance of 306±8 Ω/square.

Record Breakdown Voltage (2200 V) of GaN DHFETs on Si With 2-

In this letter, we present a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (V_BD) of AlGaN/GaN/AlGaN double heterostructure FETs on a Si (111) substrate with only 2-μm-thick AlGaN buffer. Before local Si removal, V_BD saturates at ~700 V at a gate-drain distance (L_GD) ≥ 8 μm. However, after etching away the substrate locally, we measure a record V_BD of 2200 V for the devices with L_GD = 20 μm. Moreover, from Hall measurements, we conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties.

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In this letter, we present a novel approach to enhance the breakdown voltage (<i>V</i>_BD) for AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs), grown by metal-organic chemical vapor deposition on Si (111) substrates through a silicon-substrate-removal and a layer-transfer process. Before removing the Si substrate, both buffer isolation test structures and DHFET devices showed a saturation of <i>V</i>_BD due to the electrical breakdown through the Si substrate. We observed a <i>V</i>_BD saturation of 500 V for isolation gaps larger than 6 μm . After Si removal, we measured a <i>V</i>_BD enhancement of the AlGaN buffer to 1100 V for buffer isolation structures with an isolation gap of 12 μm. The DHFET devices with a gate-drain (<i>L</i>_GD) distance of 15 μm have a V_BD > 1100 V compared with ~300 V for devices with Si substrate. Moreover, from Hall measurements, we conclude that the substrate-removal and layer-transfer processes have no impact on the 2-D electron gas channel properties.

Buffer Thickness by Local Substrate Removal

AlGaN/GaN/AlGaN double heterostructure field-effect transistors (DHFET) with high breakdown voltage and low on-resistance were fabricated on silicon substrates. A linear dependency of the breakdown voltage on the buffer thickness and on the buffer Aluminium concentration was found. A breakdown voltage as high as 830 V and an on-resistance as low as 6.2 Ωmm were obtained in devices processed on 3.7 µm buffer thickness. The gate–drain spacing was 8 µm and the devices did not have any field plates.

Silicon Substrate Removal of GaN DHFETs for Enhanced (<1100 V) Breakdown Voltage

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown, and reverse-bias stress tests, and provides the following, relevant, information: 1) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the on-resistance (RON), and in a slight shift in threshold voltage; 2) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; 3)current transient measurements indicate the existence of one trap level, with activation energy of 1.03 ± 0.09 eV; and 4) we demonstrate that through the improvement of the fabrication process, it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments in off-state. Results indicate that exposure to moderate-high reverse bias (<; 250 V for LGD = 2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse voltages (typically, VDS = 260-265 V, on a device with LGD = 2 μm stressed with VGS = - 8 V) and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e., in a region where the electric field is maximum.

AlGaN/GaN/AlGaN Double Heterostructures on Silicon Substrates for High Breakdown Voltage Field-Effect Transistors with low On-Resistance

This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate. The exposure to OFF-state bias induces a significant increase in the ON-resistance (Ron) of the devices. Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) Ron-increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C-140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the Ron-increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length.

Trapping and Reliability Assessment in D-Mode GaN-Based MIS-HEMTs for Power Applications

The breakdown mechanism in GaN-based heterostructures (HFETs) grown on silicon substrate is investigated in detail by TCAD simulations and silicon substrate removal technique. High-voltage electrical measurements show that the breakdown voltage saturates for larger gate-drain distances. This failure mechanism is dominated by the avalanche breakdown in the Si substrate. High-voltage TCAD simulations of AlGaN/GaN/Si substrate structures show higher impact ionization factor and electron density at the Si interface indicating a leakage current path where avalanche breakdown occurs. Experimentally, by etching off the Si substrate the breakdown voltage no longer saturates and linearly increases for all gate-drain gaps. We propose the silicon removal technique as a viable way to enhance the breakdown voltage of AlGaN/GaN devices grown on Si substrate.

Kinetics of Buffer-Related RON-Increase in GaN-on-Silicon MIS-HEMTs

Au-free GaN-based metal-insulator-semiconductor high electron-mobility transistors grown on 150-mm Si substrates are reported. The device characteristics for three different processes are compared: an ohmic-first and a gate-first process with Al₂O₃-only as gate dielectric and a novel approach with a bilayer gate dielectric stack consisting of Si₃N₄ and Al₂O₃. The Si₃N₄ layer was deposited in situ in the metal-organic chemical vapor deposition reactor in the same growth sequence as the rest of the epilayer stack and the Al₂O₃ layer was deposited ex situ by atomic layer deposition. Only the process with the bilayer gate dielectric results in robust devices with a breakdown voltage >600 V. The ohmic contact resistance for Au-free Ti/Al/W metallization scheme is <;1 Ω·mm. The devices show high maximum output current density (>0.4 A/mm); and low gate and drain leakage (<;10^-10 A/mm). The maximum pulsed mode drain-source current of power bars with 20 mm gate width is 8 A. The specific on-state resistance is 2.9 m Ω·cm².

Experimental and simulation study of breakdown voltage enhancement of AlGaN/GaN heterostructures by Si substrate removal

In this letter, we studied the forward bias gate breakdown mechanism on enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistors. To the best of our knowledge, it is the first time that the temperature dependence of the forward gate breakdown has been characterized. We report for the first time on the observation of a positive temperature dependence, i.e., a higher temperature leads to a higher gate breakdown voltage. Such unexpected behavior is explained by avalanche breakdown mechanism: at a high positive gate bias, electron/hole pairs are generated in the depletion region at the Schottky metal/p-GaN junction. Furthermore, at a high gate bias but before the catastrophic gate breakdown, a light emission was detected by a emission microscopy measurement. This effect indicates an avalanche luminescence, which is mainly due to the recombination of the generated electron/hole pairs.

Fabrication and Performance of Au-Free AlGaN/GaN-on-Silicon Power Devices With

This letter reports an in-depth study of the negative threshold voltage instability in GaN-on-Si metal-insulator-semiconductor high electron mobility transistors with partially recessed AlGaN. Based on a set of stress/recovery experiments carried out at several temperatures, we demonstrate that: 1) operation at high temperatures and negative gate bias (-10 V) may induce a significant negative threshold voltage shift, that is well correlated to a decrease in on-resistance; 2) this process has time constants in the range between 10-100 s, and is accelerated by temperature, with activation energy equal to 0.37 eV; and 3) the shift in threshold voltage is recoverable, with logarithmic kinetics. The negative shift in threshold voltage is ascribed to the depletion of trap states located at the SiN/AlGaN interface and/or in the gate insulator.