Nathan P. Chelstrom

Debug of the CELL Processor: Moving the Lab into Silicon

With 234 million transistors, making up 9 processing units and 3 asynchronous clock domains in a high speed design, the CELL processor clearly presents a challenge to debug work required during lab bring-up and test bring-up. Traditional multi-processing systems reap the benefit of standard system level debug practices, but as the system has moved into the silicon so must the access during bring-up. This paper explains some of the innovative debug features included in the CELL processor design that were critical for efficient bring-up in a limited access environment

Panel discussion for "have we overcome the challenges associated with SoC and multi-core testing?"

With a growing number of system-on-chip (SoC) and multi-core products entering the marketplace, innovative solutions have been created to overcome the challenges these products bring in terms of testability. Some of the challenges associated with SoC and multi-core testing are related to scan test, memory test, asynchronous interface, debug, and tester related challenges. This paper describes the particular ways the CELL processor has overcome these challenges