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Dive into the research topics where Nathan P. Chelstrom is active.

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Featured researches published by Nathan P. Chelstrom.


international test conference | 2006

Debug of the CELL Processor: Moving the Lab into Silicon

Mack W. Riley; Nathan P. Chelstrom; Mike Genden; Shoji Sawamura

With 234 million transistors, making up 9 processing units and 3 asynchronous clock domains in a high speed design, the CELL processor clearly presents a challenge to debug work required during lab bring-up and test bring-up. Traditional multi-processing systems reap the benefit of standard system level debug practices, but as the system has moved into the silicon so must the access during bring-up. This paper explains some of the innovative debug features included in the CELL processor design that were critical for efficient bring-up in a limited access environment


international test conference | 2005

Panel discussion for "have we overcome the challenges associated with SoC and multi-core testing?"

Nathan P. Chelstrom

With a growing number of system-on-chip (SoC) and multi-core products entering the marketplace, innovative solutions have been created to overcome the challenges these products bring in terms of testability. Some of the challenges associated with SoC and multi-core testing are related to scan test, memory test, asynchronous interface, debug, and tester related challenges. This paper describes the particular ways the CELL processor has overcome these challenges


Archive | 2006

Method for testing an integrated circuit device having elements with asynchronous clocks or dissimilar design methodologies

Nathan P. Chelstrom; Steven Ross Ferguson; Mack W. Riley


Archive | 2009

Dynamic frequency scaling sequence for multi-gigahertz microprocessors

Nathan P. Chelstrom; Mack W. Riley; Michael Fan Wang; Stephen Douglas Weitzel


Archive | 2005

Systems and methods for LBIST testing using isolatable scan chains

Naoki Kiryu; Mack W. Riley; Nathan P. Chelstrom


Archive | 2007

Method and apparatus for processing error information and injecting errors in a processor system

Nathan P. Chelstrom; Tilman Gloekler; Ralph C. Koester; Mack W. Riley


Archive | 2005

Apparatus and method for using eFuses to store PLL configuration data

Irene Beattie; Nathan P. Chelstrom; Matthew E. Fernsler; Mack W. Riley


Archive | 2008

Testing functional boundary logic at asynchronous clock boundaries of an integrated circuit device

Nathan P. Chelstrom; Steven Ross Ferguson; Mack W. Riley


Archive | 2008

Method and apparatus for testing a ring of non-scan latches with logic built-in self-test

Louis Bernard Bushard; Nathan P. Chelstrom; Naoki Kiryu; David John Krolak


Archive | 2005

Systems and methods for LBIST testing using commonly controlled LBIST satellites

Naoki Kiryu; Nathan P. Chelstrom; Mack Wayne Riley; Louis B. Bushard

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