John M. Cotte

Simultaneous fabrication of RF MEMS switches and resonators using copper-based CMOS interconnect manufacturing methods

This paper describes the successful concurrent fabrication of micro-electro-mechanical (MEM) electrostatic switches and resonators on the same wafer. Base processes from copper interconnect technology were used to fabricate devices allowing for easy introduction of MEMS technology into CMOS IC manufacturing. Both switches and resonators were electrically tested in a controlled ambient to determine performance and characteristics.

Pb-free solder alloys for flip chip applications

In addition to the environmental issue regarding the use of Pb-bearing solders in microelectronics applications, there is another issue associated with using Pb-bearing solders in interconnections, like flip chip solder interconnections in an advanced CMOS technology, that are near active circuits. In order to minimize the soft error rate due to alpha particle emission from Pb-bearing solder alloys, Pb-free solder alloys were studied as possible replacements for the Pb-based solders that are presently used in flip chip interconnections. A large number of solder compositions was selected for evaluation. Since all the candidate alloys were Sn-based, alternatives for the ball-limiting metallurgy (BLM) were also investigated. The physical, chemical, mechanical and electrical properties of the alloys were determined by thermal analysis, wettability testing, microhardness measurement, electrical resistivity measurement, interfacial reaction study and others. Test vehicles were also built with some selected Pb-free solder alloys with the proper BLM to evaluate integrity of the flip chip solder bump structure. Based on this study, a few candidate solder alloys were selected with a proper BLM barrier layer for flip chip applications.

High-efficiency 60 GHZ antenna fabricated using low-cost silicon micromachining techniques

In this paper, a miniature, multi-functional Si-based packaging technology which can reduce the size and cost and increase the performance of a wide range of millimeter wave systems is proposed. High density capacitors, low temperature coefficient resistors, high-Q inductors, low-loss transmission lines, filters and antennas can all be built within the Si package using standard semiconductor fabrication methods with very high manufacturing precision compared to conventional packaging technologies. Fine pitch metal bumps can be used to attach RF ICs and other components, while bonding can provide hermetic sealing where required. Vias through the Si package eliminates inductive bond wires and minimize parasitics at millimeter wave frequencies. By integrating both antenna and an RF IC in one single package, all high frequency signals are confined within the package and only baseband signals connected to the external package.

System-on-package (SOP) technology, characterization and applications

A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may range from miniaturized consumer products such as integrated function cell phones to high performance computers. SOP technology and related chip stacking challenges have been investigated and robust technology options are reported. Silicon through-vias can be fabricated using copper, tungsten, composite or alternate conductors. Via design and structure are discussed for vias in thin silicon packages mounted on a supporting substrate as well as thick silicon package that can be handled without a supporting substrate. Fine-pitch, high bandwidth wiring has been fabricated, characterized and shows greatest bandwidth for shorter interconnection distances. Fine pitch area array solder interconnections have been fabricated and characterized electrically, mechanically and with accelerated reliability testing. These fine pitch interconnections can enable the high bandwidth wiring for chip-to-chip interconnection. Integrated decoupling capacitors have been fabricated using parallel plate and trench technology. The integrated decoupling capacitors can provide under-chip, low inductance bypassing to minimize noise from simultaneous switching noise. New fine pitch, area array test technology provides a path to wafer level test for known-good-die, functional test, and burn-in for the fine pitch chip I/O. Advanced microchannel cooling can be leveraged to support high power, close proximity chips and chip stacks for cooling > 300 W/cm2. This IBM research paper describes the design, technical challenges and progress for next generation SOP technology, chip stacking, characterization, and potential new applications

113-GHz f/sub T/ graded-base SiGe HBT's

Summary form only given. A novel low-thermal cycle process was used to fabricate epitaxial SiGe-base heterojunction bipolar transistors (HBTs) with record unity current gain cutoff frequencies. The process includes an in situ phosphorus-doped polysilicon emitter which requires only a 800 degrees C-10-s anneal. A peak f/sub T/ of 113 GHz at V/sub CB/ of 1 V was obtained for an intrinsic base sheet resistance of 7 k Omega / Square Operator . >

Integrated, variable-reluctance magnetic minimotor

The use of lithography and electroplating to fabricate variable-reluctance, nearly planar, integrated minimotors with 6-mm-diameter rotors on silicon wafers is described. The motors consist of six electroplated Permalloy® horseshoe-shaped cores that surround the rotor. Copper coils are formed around each core. The Permalloy and copper electroplating baths, electroplating seed layers, and through-mask plating techniques are similar to those used to fabricate inductive thin-film heads. High-aspect-ratio optical lithography or X-ray lithography was used to form the various resist layers. The rotors were fabricated separately, released from the substrate, and then slipped onto the shaft, which was plated as part of the stator fabrication process. The fabrication processes for stator and rotor are described in this paper, and initial minimotor operation data are presented.

An alternative low resistance MOL technology with electroplated rhodium as contact plugs for 32nm CMOS and beyond

This paper addresses a critical CMOS challenge of increasing parasitic resistance by introducing electroplated rhodium (Rh) as an alternative middle-of-line (MOL) metallurgy to replace the conventional CVD tungsten (W) processes for lower contact resistance and better extendibility to 32 nm technology and beyond. Electroplating of Rh is shown to have similar to Cu superconformal filling capability, allowing us to successfully fill high aspect ratio vias (40 nm times 240 nm). Plating of 300 mm wafers with 60 nm times 290 nm vias was demonstrated using CVD or ALD ruthenium (Ru) as the seed layer. An annealing process was developed to obtain a thin Rh film resistivity of 6.5 muOmega-cm, which is 1.5 to 3X lower than the resistivity of CVD W films. Since Rh is stable in Si environment, when compared to a fast diffusing Cu, a very thin Ti/Ru layer can be implemented. Therefore we propose to use PVD Ti/ALD Ru/electroplated Rh as the alternative MOL metallurgy. With this simple liner/seed/fill stack, the overall MOL resistance is calculated to be 2x lower than the overall MOL resistance of the conventional W stacks, and slightly lower than Cu fill stacks. In addition, the ability to use a thinner liner layer than that used for Cu-base fill process, provides a greater potential for extendibility of Rh fill into future CMOS MOL generations.

113-GHz f T graded-base SiGe HBTs

A novel low-thermal cyclc proccss was used to fabricatc epitaxial SiGe-base heterojunction bipolar transistors (HBTs) with record unity current gain cutoff frequencies. The process includes an in situ phosphorus-dopcd polysilicon emitter which requires only a 800°C-10s anneal. A peak fT of 113 GHz at VCB of 1V was obtained for an intrinsic base sheet resistance of 7 kΩ/square.

Dielectric Charging in Electrostatically Actuated MEMS Ohmic Switches

MEMS switches having separate signal and actuation electrodes with different air gaps are fabricated using a copper-based CMOS interconnect manufacturing process. By using a control voltage high enough to establish metal-metal contact between the signal electrodes while avoiding contact between the dielectric-covered actuation electrodes, dielectric charging appears to be tolerable. By simultaneously measuring the conductance across the signal electrodes and the capacitance across the actuation electrodes, the conductance-force characteristic can be readily monitored and analyzed. For the present switches, the effect of polarization charge appears to be negligible, and dielectric charging is significant only after dielectric contact is made and space charge is injected.

Wafer-scale integration of sacrificial nanofluidic chips for detecting and manipulating single DNA molecules

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.