Maher Fakih

Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking

The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task became very challenging. In this paper, a model-checking based approach will be described which allows us to guarantee timing bounds of multiple Synchronous Data Flow Graphs (SDFG) running on shared-bus multicore architectures. Our approach utilizes Timed Automata (TA) as a common semantic model to represent software components (SDF actors) and hardware components of the multicore platform. These TA are explored using the UPPAAL model-checker for providing the timing guarantees. Our approach shows a significant precision improvement compared with the worst-case bounds estimated based on maximal delay for every bus access. Furthermore, scalability is examined to demonstrate analysis feasibility for small parallel systems.

SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Abstract With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER 1 targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This article will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.

State-based real-time analysis of SDF applications on MPSoCs with shared communication resources

The timing predictability of Multi-Processor System on Chip (MPSoC) platforms with hard real-time applications is much more challenging than that of traditional platforms due to their large number of shared processing, communication and memory resources. Yet, this is an indispensable challenge for guaranteeing their safe usage in safety critical domains (avionics, automotive).In this article, a real-time analysis based on model-checking is proposed. The model-checking based method allows guaranteeing timing bounds of multiple Synchronous Data Flow Application (SDFA) implementations. This approach utilizes timed automata (TA) as a common semantic model to represent WCET of software components (SDF actors) and shared communication resource access protocols for buses, DMA, private local and shared memories of the MPSoC. The resulting network of TA is analyzed using the UPPAAL model-checker for providing safe timing bounds of the implementation. Furthermore, we will show the extension of our previous system model enabling single-beat inter-processor communication style beside the burst-transfer style and provide the implementation of the complete set of TA templates capturing the considered system model.We demonstrate our approach using a multi-phase electric motor control algorithm (modeled as SDFA) mapped to Infineons TriCore-based Aurix multicore hardware platform with both the burst and single-beat inter-processor communication styles. Our approach shows a significant precision improvement (up to a percentage improvement of 300%) compared with the worst-case bound calculation based on a pessimistic analytical upper-bound delays for every shared resource access. In addition, scalability is examined to demonstrate analysis feasibility for small parallel systems, up to 40 actors mapped to 4-tiles and up to 96 actors on a 2-tiles platforms.

Exploiting Segregation in Bus-Based MPSoCs to Improve Scalability of Model-Checking-Based Performance Analysis for SDFAs

The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task becomes even more challenging, because of shared processing, communication and memory resources. Model-checking techniques are capable of verifying the performance properties of applications running on these platforms. Unfortunately, these techniques are not scalable when analyzing systems with large number of tasks and processing units. In this paper, a model-checking based approach that allows to guarantee timing bounds of multiple Synchronous Data Flow Applications (SDFA) running on shared-bus multicore architectures will be extended for a TDMA hypervisor architecture. We will improve the the number of SDFAs being analyzable by our model-checking approach by exploiting the temporal and spatial segregation properties of the TDMA architecture and demonstrate how this method can be applied.

Towards Virtual Prototyping of Synchronous Real-time Systems on NoC-based MPSoCs

NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a NoC-based designs provide a scalable and flexible communication solution for the rising number of processing cores on a single chip. To master the complexity of the software design in such a NoC-based multi-core architecture, advanced incremental integration testing solutions are required. This work presents a virtual platform based software testing and debugging approach for a synchronous application model on a 2x2 NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work. NoC-based MPSoC. We propose a development approach and a test environment that exploits the time approximation within Imperas OVP instruction accurate simulator and a functional model of the Nostrum NoC, for both software instructions and hardware clock cycles at larger time stamps called Quantum that does not sacrifice functional correctness. The functional testing environment runs the target software without running it on the real hardware platform. With the help of Nostrum NoC we can support a synchronous system execution that is reasonably fast and precise with respect to a global synchronization signal, called HeartBeat. As work in progress, this work also discusses several possible timing refinement and their possible implication on the simulation semantics and performance and how it is tackled in the future work.

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Scenario-Aware Data-Flow Graphs (SADFGs) were introduced to capture the behavior of embedded applications achieving a good trade-off between expressiveness and analyzability. On the one side, they support the timing analysis of real-time applications, especially those running on MPSoCs, due to the clean separation of computation and communication phases in their executing nodes. On the other side, SADFGs allow the expression of a more dynamic behaviors than Synchronous dataflow graphs by allowing dynamic token-rates of single nodes depending on pre-defined typical scenarios. The fact which leads to more efficiency and better throughput. In this paper, we describe the extension of a previous model-checking based real-time analysis approach to allow the analysis of timing bounds for FSM-SADFGs mapped on a shared memory multiprocessor architecture. We demonstrate our approach on an MPEG decoder application being viable to obtain the worst-case end-to-end latency of its implementation under different scenarios on a 2-tiles MPSoC.

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms

Todays Cyber-Physical Systems (CPS) are witnessing a growing complexity in terms of the number of components and computational power in order to meet the requirements of nowadays applications. For this reason and due to their energy efficiency, Multiprocessor system-on-chips (MPSoC) are becoming ubiquitous. Yet, since these systems are often used in battery-driven and/or small housing use cases, the correct configuration of their power management techniques is an important factor in system design and can be related to possible safety aspects of the system. This calls for an adequate test framework, which is able to observe the power management functionalities of CPS, even before the actual hardware platform is available. The use of virtual platforms for functional validation, that allows executing the CPSs real target platform compatible application binary code on a generic host computer, is currently being adopted by the industry. This work focuses on enhancing industrial OVP virtual platforms by a functional test framework of the power management techniques. We will demonstrate and evaluate how this framework maintains to observe the power management techniques of the system under test. The evaluation uses a Xilinx ZC702 board based on a Xilinx Zynq-7000MPSoC and its correspondent virtual platform in OVP. Results show that the functional test framework is able to analyze the different modes of operation regarding the power management techniques of the Xilinx Zynq processing system.