Kim Grüttner

Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges

Intelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults. Additionally, Virtual Prototypes (VPs) have been accepted in many areas of system development processes in the automotive industry as platforms for SW development, verification, and design space exploration. We believe that VPs will significantly contribute to the analysis of safety conditions for automotive electronics. This paper shows the advantages of such a methodology based on todays industrial needs, presents the current state of the art in this field, and outlines upcoming research challenges that need to be addressed to make this vision a reality.

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

The consideration of an embedded devices power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of todays heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project.

Non-invasive Power Simulation at System-Level with SystemC

Due to the increasing algorithmic complexity of today’s embedded systems, consideration of extra-functional properties becomes more important. Extra-functional properties like timing, power consumption, and temperature need to be validated against given requirements on all abstraction levels. For timing and power consumption at RT- and gate-level several techniques are available, but there is still a lack of methods and tools for power estimation and analyses at system and higher levels. In this paper we present an approach for non-invasive augmentation of functional SystemCTM TLM-2.0 components with power properties. The I/O behaviour of a TLM-2.0 component will be observed by a Protocol State Machine (PrSM) that generates trigger events to stimulate a Power State Machines (PSM). The PSM describes the component’s internal power states and transitions and transitions between them. Each component’s PSM is connected with a frequency and voltage dependent power model. We present first evaluation results of different IP components and compare our system-level power traces generation with state-of-the-art gate-level power simulations in terms of accuracy and simulation speed.

From RTL IP to functional system-level models with extra-functional properties

The paper presents a novel abstraction methodology for generating time- and power-annotated TLM models from synthesizable RTL descriptions. The proposed techniques allow the integration of existing RTL IP components into virtual platforms for early software development and platform design, configuration, and exploration. With the proposed approach, IP models can be natively integrated into SystemC TLM-2.0 platforms and executed 10-1000 times faster compared to state-of-the-art RTL simulators. The abstraction methodology guarantees preservation of the behaviour and timing of the RTL models. Target technology dependent power properties of IP components are represented as power state-machines and integrated into the abstracted TLM models. The experimental results show a relative error less than 10\% of the abstracted models power consumption compared to state-of-the-art RTL power simulators. The evaluation has been performed on RTL IP components with different characteristics and demonstrates the effectiveness of the presented abstraction methodology.

Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking

The timing predictability of embedded systems with hard real-time requirements is fundamental for guaranteeing their safe usage. With the emergence of multicore platforms this task became very challenging. In this paper, a model-checking based approach will be described which allows us to guarantee timing bounds of multiple Synchronous Data Flow Graphs (SDFG) running on shared-bus multicore architectures. Our approach utilizes Timed Automata (TA) as a common semantic model to represent software components (SDF actors) and hardware components of the multicore platform. These TA are explored using the UPPAAL model-checker for providing the timing guarantees. Our approach shows a significant precision improvement compared with the worst-case bounds estimated based on maximal delay for every bus access. Furthermore, scalability is examined to demonstrate analysis feasibility for small parallel systems.

SystemC-based modelling, seamless refinement, and synthesis of a JPEG 2000 decoder

This paper will exemplarily describe and evaluate the OSSS methodology for embedded hardware/software systems and its use in a JPEG 2000 decoder case-study. The OSSS approach defines a design flow starting from an Application Model providing a rich subset of SystemCTM/C++ augmented with specific OSSS language concepts. It can be used to identify the most promising parallel structure by comparing different design alternatives. A clearly defined refinement process leads to the Virtual Target Architecture (VTA) Model. These refinements enable an analysis of the system behaviour at cycle-accurate granularity and support the exploration of different target architectures for the JPEG 2000 decoder. VTA models can be used as direct input for the FOSSY synthesis tool, which performs an automatic transformation into implementation models; that is to generate VHDL code for hardware, C/C++ for software, and platform configuration files for the target technology.

Modelling Program-State Machines in SystemC™

The Program-State Machine (PSM) unifies the concepts of hierarchical concurrent finite-state machines, dataflow graphs and imperative programming languages in a single model of computation. It is used as the foundation of the SpecC System Level Design Language. This paper demonstrates the obstacles and proposes an implementation of the PSM model of computation using SystemC. It is shown that this implementation overcomes some fundamental obstacles when using SystemC for System Level Design. Furthermore, we show the applicability of our PSM implementation by porting a JPEG encoder design originally implemented in SpecC. A comparison of model execution time is very promising and shows that our proposed approach is competitive with a native SpecC model execution.

An ESL timing & power estimation and simulation framework for heterogeneous socs

Consideration of an embedded systems timing behaviour and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. But prediction of the composed system behaviour can hardly be made without considering all system components. In this paper we present an ESL framework for timing and power aware rapid virtual system prototyping of heterogeneous SoCs consisting of software, custom hardware and 3rd party IP components. Our proposed flow combines system-level timing and power estimation techniques with platform-based rapid prototyping. Virtual executable proto-types are generated from a functional C/C++ description, which then allows to study different platforms, mapping alternatives, and power management strategies. We propose an efficient code annotation technique for timing and power, that enables fast host execution and collection of power traces, based on domain-specific workload scenarios.

CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties

The increasing processing power of todays HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. The paper presents the CONTREX European project and its preliminary results. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels.

Towards a synthesis semantics for systemC channels

In this paper we propose a synthesis semantics for SystemC™ channels, which contribute to a clear separation between computation (algorithm) and communication, whereas communication related parts are modelled through either primitive or hierarchical channels. We present a synthesisable replacement for SystemC primitive channels that allows deterministic access scheduling and user-constrained refinement for HW/HW and HW/SW communication. We demonstrate the feasibility of our approach through synthesis and exploration of a communication intensive packet switch design under consideration of different configurations and communication refinements.