Mahesh Kumar Adimulam

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture

In this paper, a design for low power flash ADC with configurable resolution is proposed. A novel sub flash architecture is employed to achieve variable resolution as well as to switch the unused parallel voltage comparators and resistor bias circuit to standby mode leading to the consumption of only leakage power. The ADC is capable of operating at 4-bit, 6-bit and 8-bit precision and at a supply voltage of 1.0V, it consumes 48mW at 8-bit, 36mW at 6-bit and 15mW at 4-bit resolution. The proposed ADC have been designed, compared with conventional flash ADC and verified for post layout simulations in standard 65nm CMOS technology.

Ultra Low Power Programmable Wireless ExG SoC Design for IoT Healthcare System.

An 8-channel ultra low power programmable wireless ExG (ECG, EMG and EEG) system-on-chip (SoC) design for bio-signal processing applications is presented in this paper. The proposed design consists of a capacitive coupled programmable gain instrumentation amplifier (CC-PGIA) with an improved transconductance of amplifier. A 12-bit programmable hybrid SAR-Cyclic analog-to-digital converter (ADC) is introduced for improved performance and low power consumption that consists of a 6-bit SAR ADC (SADC) followed by a 6-bit cyclic ADC (CADC). The remaining blocks implemented in the SoC are programmable low pass filter (PLPF), programmable wireless transmitter (PWT), power management unit (PMU) and a digital block. The proposed programmable wireless ExG (PW-ExG) design is implemented in 180 nm standard CMOS process with a core area of 4 mm2. The performance parameters are found to be, power consumption of 286 µW @ 0.6 V supply voltage, input referred noise voltage of 0.96 µVrms over 0.5 Hz–1 kHz range, gain of 30–65 dB and signal-to-noise-and-distortion ratio (SNDR) of 69.2 dB.

A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements

A low power Programmable Analog Front End (PAFE) for biopotential measurements is presented in this paper. The PAFE circuit processes electrocardiogram (ECG), electromyography (EMG) and electroencephalogram (EEG) signals with higher accuracy. It consists mainly of improved transconductance programmable gain instrumentational amplifier (PGIA), programmable high pass filter (PHPF), and second order low pass filter (SLPF). A 15-bit programmable 5-stage successive approximation analog-to-digital converter (SAR-ADC) is implemented for improving the performance, whose power consumption is reduced due to multiple stages and by OTA/Comparator sharing technique between the stages. The power consumption is further reduced by operating the analog portion of PAFE on 0.5V supply voltage and digital portion on 0.3V supply voltage generated internally through a voltage regulator. The proposed low power PAFE has been fabricated in 180nm standard CMOS process. The performance parameters of PAFE in 15-bit mode are found to be, gain of 31–70 dB, input referred noise of 1.15 µVrms, CMRR of 110 dB, PSRR of 104 dB, and signal-to-noise distortion ratio (SNDR) of 83.5dB. The power consumption of the design is 1.1 µW @ 0.5 V supply voltage and it occupies a core silicon area of 1.2 mm2.

A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications

In this paper, a novel ultra-low power, programmable gain instrumentation amplifier (PG-IA) for biomedical signal processing applications is presented. The fully differential PG-IA employs a new rail-to-rail current mirror input pair with three stage indirect compensation (RR-CMI) amplifier. The proposed design improves the dc offset by implementing a fully symmetrical structure and is further reduced by using one time calibration after power up. The accuracy of the common mode feedback circuit in the design is analyzed by implementing the same on both p-side and n-side loads. Power consumption is reduced by operating the fully differential amplifier on 1 V supply and calibration & digital logic on 0.5 V supply voltage, generated from internal ultra-low power voltage regulator. The design is integrated with complete analog front end (AFE) system and performance parameters are compared with the recent state of the art designs. The overall PG-IA design is implemented in standard 180nm CMOS technology. Simulation results show the power consumption to be 0.32 µW at 1 V supply, input referred noise of 0.72 µVrms integrated over frequency range of 1 Hz – 1 KHz, SNDR of 76.8 dB, PSRR of 119 dB, CMRR of > 100 dB. The design occupies a die core area of 0.0625 mm2.

Modeling of EXG (ECG, EMG and EEG) non-idealities using MATLAB

EXG [Electrocardiography (ECG), Electromyography (EMG) and Electroencephalogram (EEG)] signals are of very low amplitude and frequency with immense diagnostic value. These signals acquire noise while travelling through electrodes, printed circuit board (PCB), integrated circuits (ICs), etc. and thus their detection and interpretation is a challenge in biomedical engineering. This paper presents MATLAB Simulink environment for an integrated EXG electronic measuring system that allows designers to analyze the time/frequency domain behavior of sensing electrodes, programmable instrumentation amplifiers (PIA), programmable band pass filter (BPF) and second order sigma delta analog to digital converter (SD-ADC). The Simulink model provides non-idealities such as sensing electrodes noise, programmable gain amplifier parameters (thermal noise, flicker noise, resistor mismatch, settling time (slew rate), dc gain, bandwidth, and voltage dynamic ranges), band pass filter parameters (noise and bandwidth), and sigma delta ADC parameters (clock jitter, capacitor mismatch, noise, settling time (slew rate), dc gain, bandwidth, and voltage dynamic ranges). A detailed simulation and implementation (Using CMOS, 180nm technology) results of the complete system is presented for both the ideal and actual performance parameters.

A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter

In this paper, a multi bandwidth 10-bit SAR analog to digital converter (ADC) with edge-combiner digital delay locked loop (DDLL) circuit for self clock generation is proposed. The ADC circuit in the proposed design avoids external clock signal for sampling and clock is generated from analog input signal for a wide range of frequency operation. The proposed ADC design is capable of operating over the input frequency range of 10Ksps to 1.8Msps with 40MHz maximum sampling clock. The proposed ADC have been designed and verified for post layout simulations in standard 65nm CMOS technology which has DNL

A multiple-bandwidth 12-bit pipelined analog to digital converter with self-clock generator

A multiple-bandwidth 12-bit pipelined analog to digital converter (ADC) with edge-combiner digital delay locked loop for self clock generation and embedded sample & hold (S/H) circuit is presented. The ADC circuit in the proposed design avoids external clock signal for sampling, by generating the clock from analog input signal for a wide range of frequency operation. The proposed design is capable of operating over the input frequency range of 10KHz to 15MHz with 150MSPS maximum sampling frequency. The proposed ADC has been verified for post layout simulations in 90nm CMOS technology which has DNL<±0.25LSB, INL<±0.5LSB, SNR of 71.5dB, SNDR of 69.1dB and maximum power consumption of 25mw at 12-bit with 150MSPS sampling frequency.

Low power, variable resolution pipelined analog to Digital converter with sub flash architecture

In this paper, a design for low power pipelined Analog to Digital converter with self configurable resolution is proposed. A novel sub flash architecture is employed to achieve variable resolution as well as to switch the unused stages to standby mode leading to the consumption of only leakage power. The ADC is capable of operating at 8-bit, 10-bit and 12-bit precision at a supply voltage of 1.2V; it consumes 25mW at 12-bit, 20mW at 10-bit and 15mW at 8-bit resolution. The sampling frequency ranges upto 150Msps, and the ADC has a DNL &#60; ±0.25LSB, INL &#60; ±0.5LSB, SNR of 71.5dB and SNDR of 69.1dB for 12-bit operation. The performance of the ADC is verified in post layout simulations at 65nm technology node.