N. Moorthy Muthukrishnan

Design of Prefix-Based Optimal Reversible Comparator

This paper presents a design of prefix grouping based reversible comparator. Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. The proposed reversible comparator design consists of three stages. The first stage consists of a 1-bit comparator where two outputs, gi indicating Ai >; Bi and ei indicating Ai = Bi, are generated for ith operand bits. The outputs of 1-bit comparator stage are grouped in the second stage using prefix grouping and the final outputs G indicating A >; B and E indicating A=B are generated. In the last stage the outputs of second stage i.e. G and E are used to generate L signal indicating A <; B. The proposed 64-bit comparator design results in 63% reduced quantum delay, 21% reduced quantum cost and 16% reduced garbage outputs when compared with the best existing design of tree based comparator.

A Modified Twin Precision Multiplier with 2D Bypassing Technique

This paper presents a twin precision multiplier with modified 2-D bypass Logic. The multiplier can perform one 8-bit multiplication or two 4-bit multiplications. The multiplier structure is modified by adding a 2-dimensional modified bypassing logic resulting in reduction in dynamic power as well the delay. Simulation results indicate that with a marginal increase in area, the proposed twin precision multiplier achieves an improvement of 25.5% in delay and up to 29% reduction of power-delay product when compared to existing designs.

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block

An Increment/Decrement circuit is a common building block in many digital systems like address generation unit which are used in micro controllers and microprocessors. Similarly 2s complement and priority encoder circuits are used in many applications. This paper presents an improvement to the decision block of the existing INC/DEC architectures. This improvement results in up to 48% reduced delay and 50% reduced power delay product. This paper also proposes a reconfigurable INC/DEC/2s complement/Priority encoder circuit which uses the new proposed decision blocks.

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths

Algorithms based Media applications operate on operands of varying data lengths. Although much work has been done in designing adder and multiplier architectures which operate on varying data lengths, there has been little work on implementing other operations like increment/decrement, 2s complement etc. This paper presents an architecture which can perform increment/decrement/2s complement/priority-encode operations on varying data lengths. A 32-bit implementation of the proposed multifunctional architecture is presented, which can operate on four 8-bit operands, two 16-bit operands or one 32-bit operand.

A Prefix Based Reconfigurable Adder

This paper presents a prefix-based reconfigurable adder. The coarse grained reconfigurable adder uses 8-bit carry generation block as a single unit. Eight such units along with the controlled-carry combination logic (prefix based), are used to form a 64-bit adder. The adder can perform one 64-bit addition, two 32-bit, four 16-bit, and eight 8-bit additions. The adder structure is modified resulting in low fan-out. Simulation results indicate that with a marginal increase in delay, the proposed prefix based reconfigurable adder results in up to 27% power delay product reduction when compared to existing design.

A Unified Architecture for BCD and Binary Adder/Subtractor

The need to have hardware support for decimal arithmetic is increasing in recent years because of the growth in the decimal data processing in commercial, financial and internet based applications. In this paper a new architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented that can be reconfigured to perform binary addition/subtraction. The architecture is mainly designed, keeping in mind the signed magnitude format. The proposed architecture avoids the usage of additional 2s complement and 10s complement circuitry, for correcting the results to sign magnitude format. The architecture is run-time reconfigurable to facilitate both BCD and Binary operations. Simulation results show that the proposed architecture is 13.6% better in terms of delay than the existing design.

Design of CNFET based ternary comparator using grouping logic

This paper presents a design of ternary magnitude comparator based on the CNFET (Carbon Nanotube Field Effect Transistor) ternary logic gates. Ternary logic is a promising alternative to conventional logic design because of its energy efficiency. This energy efficiency is achieved due to the reduced circuit overhead for ternary logic when compared to the conventional binary logic. The comparator design is based on prefix based design and combines ternary and binary logic gates for optimized implementation. The proposed comparator has been implemented and simulated using SPICE. Simulations results indicate that the proposed 1-bit comparator consumes 0.65μW power and has a delay of 21ps. The simulation results for comparators with different operand lengths are also presented.

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture

In this paper, a design for low power flash ADC with configurable resolution is proposed. A novel sub flash architecture is employed to achieve variable resolution as well as to switch the unused parallel voltage comparators and resistor bias circuit to standby mode leading to the consumption of only leakage power. The ADC is capable of operating at 4-bit, 6-bit and 8-bit precision and at a supply voltage of 1.0V, it consumes 48mW at 8-bit, 36mW at 6-bit and 15mW at 4-bit resolution. The proposed ADC have been designed, compared with conventional flash ADC and verified for post layout simulations in standard 65nm CMOS technology.

Higher radix sparse-2 adders with improved grouping technique

When high speed addition is required for arithmetic circuits, either prefix or sparse-tree adder methodology is preferred, depending on the design constraints. Higher radix prefix adders have less logic depth but increased wiring and logic cells, whereas sparse adders have less wiring tracks, but increased logic depth. This paper presents a hybrid grouping technique for radix-4 sparse-2 adders which results in reduced wiring when compared to the existing radix-4 sparse-2 design while maintaining the advantage of both prefix and sparse techniques. Simulation results show that there is a reduction in power-delay product in radix-4 sparse-2 implementation with the proposed modification when compared to the existing implementations.

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders

Reversible computing has emerged as promising technology having its applications in quantum computing, nanotechnology and optical computing. This paper presents design and analysis of reversible ripple, prefix and prefix ripple hybrid adders. Firstly an analysis and comparison of all the existing reversible ripple carry adders is presented. The reversible ripple carry adders are characterized by high quantum depth, low quantum cost and/or low garbage outputs and ancilla inputs bits. Secondly design methodology for reversible prefix adders is presented. The reversible prefix adders are characterized by low quantum depth, high quantum cost and/or high garbage outputs and ancilla inputs bits. Finally design of the proposed reversible prefix-ripple hybrid adders is presented and comparison of the different parameters of reversible ripple, prefix and prefix-ripple hybrid adders is illustrated.