Sreehari Veeramachaneni

A Prefix Based Reconfigurable Adder

This paper presents a prefix-based reconfigurable adder. The coarse grained reconfigurable adder uses 8-bit carry generation block as a single unit. Eight such units along with the controlled-carry combination logic (prefix based), are used to form a 64-bit adder. The adder can perform one 64-bit addition, two 32-bit, four 16-bit, and eight 8-bit additions. The adder structure is modified resulting in low fan-out. Simulation results indicate that with a marginal increase in delay, the proposed prefix based reconfigurable adder results in up to 27% power delay product reduction when compared to existing design.

A Unified Architecture for BCD and Binary Adder/Subtractor

The need to have hardware support for decimal arithmetic is increasing in recent years because of the growth in the decimal data processing in commercial, financial and internet based applications. In this paper a new architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented that can be reconfigured to perform binary addition/subtraction. The architecture is mainly designed, keeping in mind the signed magnitude format. The proposed architecture avoids the usage of additional 2s complement and 10s complement circuitry, for correcting the results to sign magnitude format. The architecture is run-time reconfigurable to facilitate both BCD and Binary operations. Simulation results show that the proposed architecture is 13.6% better in terms of delay than the existing design.

A New Design of an N-Bit Reversible Arithmetic Logic Unit

With the advent of nanotechnology, transistors are getting smaller and growing in number according to Moores Law. With this, the issue of heat dissipation is becoming of greater concern to researchers as the transistor heat dissipation reaches the Land Auer limit. Reversible logic is predicted to be an alternative to conventional computing due to lesser energy dissipation and exponentially faster problem-solving capacity. This paper introduces the design of a reversible ripple-carry adder using a mix of the well-known NCV library and the recently introduced NCV-|v1 library, with the assumption of a four-level quantum system. The results for the proposed adder are compared with previous ripple-carry adder designs. It then explores the design of a cost-optimized reversible ALU by modifying the above adder. Finally, a comparison of the proposed ALU is made with one of the latest reversible ALU designs.

A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units

In floating point addition unit, adder and normalization decides the critical path delay. By predicting the shift amount prior to the adders output the delay introduced by the normalization can be reduced. This prediction is done using a technique called Leading Zero Anticipator (LZA). LZA algorithms are divided into exact and inexact categories. Most of the existing algorithms are inexact in nature which predicts the shift amount with a possible error of 1 bit. So, these inexact LZA algorithms need an error detection circuit. This paper proposes an error detection logic implemented in parallel with adder and using a part hardware of LZA resulting in reduction of both area and power consumption by 35%-39% and 44%-48% respectively when compared with that of general LZA and error detection circuit.

Bluetooth and Wi-Fi controlled rescue robots

The unexpected magnitude and scale of natural and human-induced disasters have impelled the search and rescue teams around the world to seek for newer and more innovative equipments to enhance their efficiency. Earthquakes, Cyclones, tsunamis and other natural disasters leave the terrain not only difficult for navigation, but also dangerous for human search and rescue teams. Human rescue teams are painfully slow and sometimes need extreme caution. The problem calls for a fast and effective rescuing system. Robots have suddenly started seeking attention for their application in this field. This paper addresses the problems faced by rescue teams and how a Bluetooth or Wi-Fi controlled robot can efficiently help in saving more number of people struggling in the rubble of the collapsed buildings in case of natural disasters. The paper also highlights the advantage of using Bluetooth or any other Wireless technology controlled Robots over the currently employed tele or remote controlled robots. The proposed Robot with slight modifications can also be used for navigation in places like coal mines and nuclear plants where human search is a bit risky and dangerous.

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture

In this paper, a design for low power flash ADC with configurable resolution is proposed. A novel sub flash architecture is employed to achieve variable resolution as well as to switch the unused parallel voltage comparators and resistor bias circuit to standby mode leading to the consumption of only leakage power. The ADC is capable of operating at 4-bit, 6-bit and 8-bit precision and at a supply voltage of 1.0V, it consumes 48mW at 8-bit, 36mW at 6-bit and 15mW at 4-bit resolution. The proposed ADC have been designed, compared with conventional flash ADC and verified for post layout simulations in standard 65nm CMOS technology.

Towards realizing variable resolution analog to digital converters

In this paper, the idea of variable resolution ADCs is proposed and implemented for all types of ADC architectures. A novel peak-detector circuit is employed to achieve variable resolution as well as to switch the unused sections of the ADCs to standby mode. Linear reduction in resolution leads to exponential reduction in power. The ADCs are capable of operating at 4–12 bit precision at a supply voltage of 2.5V. The sampling frequency ranges from 1.8MSPS to 1.2 GSPS that depends on ADC topologies. Variable-resolution flash, semi — flash, pipelined and SAR ADCs operating at a maximum resolution of 8-bit, 12-bit, 12bit, 10-bit respectively have been designed and verified for post layout simulations in standard 65nm CMOS technology.

Floating point adder/subtractor units realization by efficient arithmetic circuits

Floating point adder/subtractor units like fused floating point adder, triple path floating point adder, etc., involve exponent comparison/subtraction, mantissa addition/subtraction and incrementing values while rounding as basic operations. To realize these operations, efficient arithmetic units like comparators, adders, subtractors, and incrementers are vital. In this paper an efficient design of an adder and a design methodology for 2s complement block is proposed which helps in design of floating point units.

A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter

In this paper, a multi bandwidth 10-bit SAR analog to digital converter (ADC) with edge-combiner digital delay locked loop (DDLL) circuit for self clock generation is proposed. The ADC circuit in the proposed design avoids external clock signal for sampling and clock is generated from analog input signal for a wide range of frequency operation. The proposed ADC design is capable of operating over the input frequency range of 10Ksps to 1.8Msps with 40MHz maximum sampling clock. The proposed ADC have been designed and verified for post layout simulations in standard 65nm CMOS technology which has DNL

A multiple-bandwidth 12-bit pipelined analog to digital converter with self-clock generator

A multiple-bandwidth 12-bit pipelined analog to digital converter (ADC) with edge-combiner digital delay locked loop for self clock generation and embedded sample & hold (S/H) circuit is presented. The ADC circuit in the proposed design avoids external clock signal for sampling, by generating the clock from analog input signal for a wide range of frequency operation. The proposed design is capable of operating over the input frequency range of 10KHz to 15MHz with 150MSPS maximum sampling frequency. The proposed ADC has been verified for post layout simulations in 90nm CMOS technology which has DNL<±0.25LSB, INL<±0.5LSB, SNR of 71.5dB, SNDR of 69.1dB and maximum power consumption of 25mw at 12-bit with 150MSPS sampling frequency.