M. B. Srinivas

New improved 1-bit full adder cells

The 1-bit full adder is a very important component in the design of application specific integrated circuits. In this paper, authors propose three new 1-bit full adders having a delay of 2-transistor (2T) using existing XOR and XNOR gates. The power consumption, delay and area of these new full adders are compared with existing ones and the results appear to be promising. The combination of low power, low transistor count and lesser delay makes the new full adders a viable option for efficient design.

CNFET based ternary magnitude comparator

Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper, a ternary magnitude comparator design based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented. This design eliminates the usage of complex ternary decoder which is a part of existing designs. Elimination of decoder results in reduction of delay and power. Simulations of proposed and existing designs are done on HSPICE and results proves that the proposed 1-bit comparator consumes 81% less power and shows delay advantage of 41.6% compared to existing design. Further a methodology to extend the 1-bit comparator design to n-bit comparator design is also presented.

Design of Prefix-Based Optimal Reversible Comparator

This paper presents a design of prefix grouping based reversible comparator. Reversible computing has emerged as promising technology having its applications in emerging technologies like quantum computing, optical computing etc. The proposed reversible comparator design consists of three stages. The first stage consists of a 1-bit comparator where two outputs, gi indicating Ai >; Bi and ei indicating Ai = Bi, are generated for ith operand bits. The outputs of 1-bit comparator stage are grouped in the second stage using prefix grouping and the final outputs G indicating A >; B and E indicating A=B are generated. In the last stage the outputs of second stage i.e. G and E are used to generate L signal indicating A <; B. The proposed 64-bit comparator design results in 63% reduced quantum delay, 21% reduced quantum cost and 16% reduced garbage outputs when compared with the best existing design of tree based comparator.

Analyzing N-Curve Metrics for Sub-Threshold 65nm CMOS SRAM

This paper examines the usefulness of N-curve metrics for a 65 nm SRAM cell operating in sub-threshold region. Various N-curve metrics are evaluated with changing power supply voltage, temperature, cell ratios, pull up ratios and oxide thickness. N-curve metrics are also evaluated considering the effect of intra die and inter die random threshold voltage variations. Results indicate that N-curve method provides better metrics in terms of SINM and WTI to assess the stability of SRAM operating in sub-threshold region and enables complete functional analysis.

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block

An Increment/Decrement circuit is a common building block in many digital systems like address generation unit which are used in micro controllers and microprocessors. Similarly 2s complement and priority encoder circuits are used in many applications. This paper presents an improvement to the decision block of the existing INC/DEC architectures. This improvement results in up to 48% reduced delay and 50% reduced power delay product. This paper also proposes a reconfigurable INC/DEC/2s complement/Priority encoder circuit which uses the new proposed decision blocks.

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths

Algorithms based Media applications operate on operands of varying data lengths. Although much work has been done in designing adder and multiplier architectures which operate on varying data lengths, there has been little work on implementing other operations like increment/decrement, 2s complement etc. This paper presents an architecture which can perform increment/decrement/2s complement/priority-encode operations on varying data lengths. A 32-bit implementation of the proposed multifunctional architecture is presented, which can operate on four 8-bit operands, two 16-bit operands or one 32-bit operand.

A Prefix Based Reconfigurable Adder

This paper presents a prefix-based reconfigurable adder. The coarse grained reconfigurable adder uses 8-bit carry generation block as a single unit. Eight such units along with the controlled-carry combination logic (prefix based), are used to form a 64-bit adder. The adder can perform one 64-bit addition, two 32-bit, four 16-bit, and eight 8-bit additions. The adder structure is modified resulting in low fan-out. Simulation results indicate that with a marginal increase in delay, the proposed prefix based reconfigurable adder results in up to 27% power delay product reduction when compared to existing design.

A Unified Architecture for BCD and Binary Adder/Subtractor

The need to have hardware support for decimal arithmetic is increasing in recent years because of the growth in the decimal data processing in commercial, financial and internet based applications. In this paper a new architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented that can be reconfigured to perform binary addition/subtraction. The architecture is mainly designed, keeping in mind the signed magnitude format. The proposed architecture avoids the usage of additional 2s complement and 10s complement circuitry, for correcting the results to sign magnitude format. The architecture is run-time reconfigurable to facilitate both BCD and Binary operations. Simulation results show that the proposed architecture is 13.6% better in terms of delay than the existing design.

Design of CNFET based ternary comparator using grouping logic

This paper presents a design of ternary magnitude comparator based on the CNFET (Carbon Nanotube Field Effect Transistor) ternary logic gates. Ternary logic is a promising alternative to conventional logic design because of its energy efficiency. This energy efficiency is achieved due to the reduced circuit overhead for ternary logic when compared to the conventional binary logic. The comparator design is based on prefix based design and combines ternary and binary logic gates for optimized implementation. The proposed comparator has been implemented and simulated using SPICE. Simulations results indicate that the proposed 1-bit comparator consumes 0.65μW power and has a delay of 21ps. The simulation results for comparators with different operand lengths are also presented.

Efficient Modulo (2k±1) Binary to Residue Converters

In this paper, the design of a binary to residue converter architecture based on {2k-1, 2k 2k+l} modulo set is presented. New highly-parallel schemes using (p,2) compressors are described for computing the integer modulo operation (X mod m), where m is restricted to the values 2kplusmn1, for any value of k>1 and X is a 16-bit or a 32-bit number For efficient design, novel 3-2, 4-2 and 5-2 compressors are illustrated and are used as the basic building blocks for the proposed converter designs. The resulting circuits are compared, both qualitatively and quantitatively, in standard CMOS cell technology, with the existing circuits. The results show that the proposed architectures are faster and use lesser hardware than similar circuits known making them a viable option for efficient design