Makoto Hatakenaka
Mitsubishi
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Publication
Featured researches published by Makoto Hatakenaka.
IEEE Journal of Solid-state Circuits | 1999
Akira Yamazaki; Tadato Yamagata; Makoto Hatakenaka; Atsushi Miyanishi; Isao Hayashi; Shigeki Tomishima; Atsuo Mangyo; Yoshio Yukinari; Takashi Tatsumi; Masashi Matsumura; Kazutami Arimoto; Michihiro Yamada
This paper describes a slight-boost scheme to improve a transistor performance in system large-scale integrated circuits, which integrate logic circuits and 1-Tr/1-C DRAMs. In this scheme, an embedded SDRAM core has been developed for graphic and multimedia applications. Its maximum operating frequency is 166 MHz, with a peak data rate of 5.3 GB/s. As well, a fast row-address access time of 22 ns has been achieved. The SDRAM core has been fabricated by means of a 0.3-/spl mu/m quad-polysilicon, triple metal, triple-well CMOS process. This SDRAM core has a block write function, enhanced by a multiselect block write scheme, and a synchronous direct memory-access test circuit has been implemented to reduce the number of test pads.
Archive | 1998
Tadato Yamagata; Akira Yamazaki; Shigeki Tomishima; Yoshio Yukinari; Makoto Hatakenaka; Atsushi Miyanishi
Archive | 2002
Takekazu Yamashita; Makoto Hatakenaka; Manabu Miura
Archive | 1997
Makoto Hatakenaka; Akira Yamazaki; Shigeki Tomishima; Tadato Yamagata
Archive | 1995
Yukio Miyazaki; Takenori Okitaka; Makoto Hatakenaka; Junji Mano
Archive | 1994
Makoto Hatakenaka
Archive | 2001
Manabu Miura; Makoto Hatakenaka
Archive | 2002
Manabu Miura; Makoto Hatakenaka; Takekazu Yamashita
Archive | 1998
Tadato Yamagata; Makoto Hatakenaka; Shigeki Tomishima; Akira Yamazaki
Archive | 1997
Manabu Miura; Makoto Hatakenaka
