Shigeki Tomishima

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty.

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q/sub s/) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-/spl mu/m CMOS process. The chip size is 7.9/spl times/16.7 mm/sup 2/ and cell size is 1.35/spl times/2.8 /spl mu/m/sup 2/.

An experimental 256-Mb DRAM with boosted sense-ground scheme

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAMs to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (boosted sense-ground) scheme for data retention and FOGOS (folded global and open segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm/sup 2/ and a performance of 34 ns access time. >

Circuit design techniques for low-voltage operating and/or giga-scale DRAMs

As use of battery-operated machines, such as hand-held computers and PDAs, becomes wider, low-voltage/low-power DRAMs are required. Low-voltage technologies are also required in giga-scale DRAMs with scaled-down voltage. This paper describes low-voltage circuit design techniques to meet these demands.

A long data retention SOI-DRAM with the body refresh function

We have proposed a body refresh function and circuits for SOI DRAMs. The body refresh utilizes a swinging of the bit line and gives stable body potential, long dynamic data retention time and low power consumption without any increase in the chip area.

SOI-DRAM circuit technologies for low power high speed multi-giga scale memories

New SOI-DRAM circuits were proposed and described. The body bias controlling technique, especially super body-synchronous sensing, is found to be suitable for low voltage operation. A new type of redundancy enables Icc2 reduction and promises high yield against the increasing standby current failure.

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs

Proposes an advanced DRAM array driving technique which can achieve low-voltage operation, a well-synchronized sensing and equalizing method. This method sets the DRAM array free from the body effect, achieves a small influence of the short channel effect, and reduces the leakage current. The sense and restore amplifier and equalizer can operate rapidly under a low-voltage operating condition such as 1.0 V V/sub CC/. Therefore, one can make determining the V/sub th/ easy for the satisfaction of the high-speed, the low-power dissipation, and a simple device structure. The well-synchronized sensing and equalizing method is applicable to low-voltage operating DRAMs with capacity of 256 Mbits and more. >

A 1.0 V 230 MHz column-access embedded DRAM macro for portable MPEG applications

Previous embedded DRAMs (eDRAMs) have the dual ports on the sense amplifier and wide I/O buses on memory arrays for high data rate in graphic controller chips. This causes decreased cell efficiency and increased power consumption in burst operation compared to commodity DRAM. This eDRAM macro provides the low power consumption and small die needed in portable multi media equipment with MPEG logic, such as video phone, video camera, and personal digital assistant (PDA). To incorporate 0.13 μm logic technology for low power, the power supply is reduced to 1.0 V for logic and 2.5 V for other circuitry. This paper describes realizing fast memory access even at such low voltage.

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications

This paper describes a 32-Mb embedded DRAM macro fabricated using 0.13-/spl mu/m triple-well 4-level Cu embedded DRAM technology, which is suitable for portable equipment of MPEG applications. This macro can operate 230-MHz random column access even at 1.0-V power supply condition. The peak power consumption is suppressed to 198 mW in burst operation. The power-down standby mode, which suppresses the leakage current consumption of peripheral circuitry, is also prepared for portable equipment. With the collaboration of array circuit design and the fine Cu metallization technology, macro size of 18.9 mm/sup 2/ and cell efficiency of 51.3% are realized even with dual interface and triple test functions implemented.

A 5.3 GB/s 32 Mb embedded SDRAM core with slightly boosting scheme

A slightly boosting (SB) scheme has been proposed for improving transistor performance in system LSIs. Using this scheme, a 32 Mb embedded SDRAM core, which operates at a 166 MHz clock frequency, has been developed. The access time of the SDRAM core has also been improved, and 4 cycles of the RAS latency at 166 MHz has been achieved. The multi-select block write (MSBW) scheme is suited to the embedded SDRAM core having a wide data bus, and it improves the performance in graphic applications. The synchronous direct memory access test (SDMAT) circuit makes it easy to evaluate the embedded SDRAM core, and it realizes the 256 b multi-bit test.