Tadato Yamagata

Automatic Voltage-swing Reduction (avr) Scheme For Ultra Low Power Drams

LIntroduction Recently, low power DRAMs[l-3] are strongly needed for handheld machines. To reduce the data-retention current, the DRAMs should have 1)long data-retention time, 2)low active current for a refresh operation, and 3)low stand-by current. This paper describes new current saving techniques for the high-density DRAMs. The combination of the Voltage-DownConvertor (VDC) and Boosted-SenseGround (BSG) scheme[4] achieves the low active current b reducing

A 5.3-GB/s embedded SDRAM core with slight-boost scheme

This paper describes a slight-boost scheme to improve a transistor performance in system large-scale integrated circuits, which integrate logic circuits and 1-Tr/1-C DRAMs. In this scheme, an embedded SDRAM core has been developed for graphic and multimedia applications. Its maximum operating frequency is 166 MHz, with a peak data rate of 5.3 GB/s. As well, a fast row-address access time of 22 ns has been achieved. The SDRAM core has been fabricated by means of a 0.3-/spl mu/m quad-polysilicon, triple metal, triple-well CMOS process. This SDRAM core has a block write function, enhanced by a multiselect block write scheme, and a synchronous direct memory-access test circuit has been implemented to reduce the number of test pads.

High-speed/high-band width design methodologies for on chip DRAM core multimedia system LSIs

Recently, as multimedia LSIs have developed, the demand for high-speed/high-band width LSIs which integrate the DRAM core and logic elements (CPU etc.) have been strongly required. However, the high-speed/high-band width operation induces the large switching noise. This noise degrades a DRAMs operating margin, and especially the data retention characteristics. In this paper, we analyze the noise transmission model and propose a DRAM and logic compatible design methodology to maintain the reliability of high-speed/high-band width system LSIs. Good experimental results are obtained on the test device.