Makoto Ichida

Automated low-power technique exploiting multiple supply voltages applied to a media processor

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance,.

Introducing redundancy in field programmable gate arrays

A redundancy scheme and circuitry for field programmable gate arrays (FPGAs) are proposed. The scheme requires the modification of the wiring resource segmentation and the addition of spare rows and selector circuits. An improved yield gross product is quantitatively studied. The disadvantages caused by this architecture, such as an area overhead and speed degradation, are discussed. It is concluded that, in this redundancy scheme, the sufficient number of spare rows is one or two for practical cases and the gross yield product can be doubled at an early stage of production. The proposed scheme can be applicable to a wide range of FPGA architectures.

3.3V-5V compatible I/O circuit without thick gate oxide

A novel 3.3V-5V compatible [/O circuit is proposed and measured to be effective from the stand-point of reliability and speed. It can endure 5V input from the external chips, although it is made only with thin gate oxide designed for use under 3.3V supply voltage. A test chip is fabricated and the measured propagation delay time, tpLH and tpHL, of an output buffer are 311s and 2.5ns, respectively. Output high level, VOH, is 3.3V.

350 MHz time-multiplexed 8-port SRAM and word size variable multiplier for multimedia DSP

A multimedia DSP optimized for digital audio/video applications provides simple flexible cost-effective solution capable of GUI acceleration, MPEG2 decoding, real-time MPEG1 encoding, personal video conferencing, 28.8 kbps fax/modem, and audio/sound functions. The main frequency of the chip is 62.5 MHz and the supply voltage is 3.3 V. The chip is fabricated in 0.5 /spl mu/m triple-metal CMOS, occupies 12.8/spl times/14.0 mm/sup 2/ and is mounted in a 240 QFP package with a heat-spreader. The chip integrates high-performance custom macro blocks: an interface for Rambus DRAMs (RAC), a 37 kb time-multiplexed 8-ported SRAM, 72 b scalable datapath and single oxide 3 V/5 V I/O. The focus here is the SRAM and word-size-variable multiplier.

Fast simulated diffusion: an optimization algorithm for multi-minimum problems and its application to MOSFET model parameter extraction

A novel algorithm, fast simulated diffusion (FSD), is proposed to solve a multiminimal optimization problem on multidimensional continuous space. The algorithm performs a greedy search and a random search alternately and can find a global minimum with a practical success rate. An efficient hill-decending method for the greedy search is proposed. When the FSD is applied to a set of standard test functions, it shows an order-of-magnitude faster speed than the conventional simulated diffusion. An application of the FSD to a MOSFET parameter extraction problem is described.<<ETX>>