Fumitoshi Hatori

A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

This MPEG4 video codec implements essential functions in the MPEG4 committee draft. It consumes 60 mW at 30 MHz, 30% of the power dissipation of a conventional CMOS design. Measured power dissipation is summarized. 70% power reduction is achieved by low-power techniques at circuit and architectural levels. A 16b RISC processor provides software programmability. Binary shape decoding uses 20% of the computation power of the RISC processor at 30MHz clock, with negligible increase in chip power dissipation. Three-step hierarchical motion estimation reduces power dissipation.

Introducing redundancy in field programmable gate arrays

A redundancy scheme and circuitry for field programmable gate arrays (FPGAs) are proposed. The scheme requires the modification of the wiring resource segmentation and the addition of spare rows and selector circuits. An improved yield gross product is quantitatively studied. The disadvantages caused by this architecture, such as an area overhead and speed degradation, are discussed. It is concluded that, in this redundancy scheme, the sufficient number of spare rows is one or two for practical cases and the gross yield product can be doubled at an early stage of production. The proposed scheme can be applicable to a wide range of FPGA architectures.

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously.

A single-chip CMOS Bluetooth transceiver with 1.5MHz IF and direct modulation transmitter

A single-chip Bluetooth transceiver in 0.18/spl mu/m CMOS integrates a direct VCO modulation transmitter and 1.5MHz-IF receiver to reduce power consumption and cost. The receiver achieves a sensitivity of -77dBm and transmitting power of +4dBm.

350 MHz time-multiplexed 8-port SRAM and word size variable multiplier for multimedia DSP

A multimedia DSP optimized for digital audio/video applications provides simple flexible cost-effective solution capable of GUI acceleration, MPEG2 decoding, real-time MPEG1 encoding, personal video conferencing, 28.8 kbps fax/modem, and audio/sound functions. The main frequency of the chip is 62.5 MHz and the supply voltage is 3.3 V. The chip is fabricated in 0.5 /spl mu/m triple-metal CMOS, occupies 12.8/spl times/14.0 mm/sup 2/ and is mounted in a 240 QFP package with a heat-spreader. The chip integrates high-performance custom macro blocks: an interface for Rambus DRAMs (RAC), a 37 kb time-multiplexed 8-ported SRAM, 72 b scalable datapath and single oxide 3 V/5 V I/O. The focus here is the SRAM and word-size-variable multiplier.

Analysis of signal to noise ratio of photoconductive layered solid-state imaging device

The signal to noise ratio of the photoconductive layered solid-state imaging device (PSID) has been theoretically derived. In this analysis the noise suppression effect due to residual signal electrons in the storage diode after read-out operation, the optical shot noise, and the fluctuation of the number of transferred signal electrons due to incomplete readout signal electrons were considered. The obtained result showed good agreement to the experimental result. >

Throughput Enhancement in Electron Beam Direct Writing by Multiple-cell Shot Technique for Logic Devices

This paper reports a new pattern design method improving the throughput of the character projection electron beam direct writing (CP-EBDW) lithography for cell-based logic devices. The shot count decreases to approximately one fifth in a 90 nm CMOS technology by assembling the standard cells (SCs) in the physical design stage and exposing them at a time with multiple-cell shot technique. The operating frequency degradation of the logic devices is less than 5 %

A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter

The frequency drift of an open-loop PLL is an issue for direct modulation applications such as Bluetooth transceivers. The drift mainly comes from the temperature variation of the VCO during the TX operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through full-chip thermal analysis. Moreover, a novel temperature-compensated VCO by employing a new biasing scheme is proposed. The combination of these two techniques enables power reduction of the transmitter by 33% without sacrificing performance.

Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI

The module-wise dynamic voltage and frequency scaling (MDVFS) scheme is applied to a single-chip H.264/MPEG-4 audio/visual codec LSI. The power consumption of the target module with controlled supply voltage and frequency is reduced by 40% in comparison with the operation without voltage or frequency scaling. The consumed power of the chip is 63 mW in decoding QVGA H.264 video at 15 fps and MPEG-4 AAC LC audio simultaneously. This LSI keep operating continuously even during the voltage transition of the target module by introducing the newly developed dynamic de-skewing system (DDS) which watches and control the clock edge of the target module.

A low-IF CMOS single-chip Bluetooth EDR transmitter with digital I/Q mismatch trimming circuit

A single-chip low-IF transmitter for the Bluetooth enhanced data rate (max. 3Mbps) was fabricated in 0.18-/spl mu/m CMOS process. A quantitative study on the relation between the VCO pulling, intermediate frequency, and the linearity of the PA shows that the 1MHz-IF is the best solution. By a digital DC offset cancellation and I/Q mismatch trimming techniques, the LO and image signal leakages are suppressed below -40dBc and -50dBc, respectively.