Yuichiro Ishii

A novel MNOS technology using gate hole injection in erase operation for embedded nonvolatile memory applications

A novel MNOS memory with gate hole injection in erase operation has been demonstrated for embedded nonvolatile memory applications. Superior characteristics with 10/spl mu/sec programming and 10msec erasing speed were obtained as compared with conventional MONOS structures. In addition, we found that the localized interface trap at source side region was generated by excess holes during erasing cycle and could be suppressed by Lg scaling. This result shows the good scalability of this technology.

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Showing that the worst minimum operating voltage (Vmin) of an 8T dual-port (DP) SRAM is determined by the write/read-disturbing condition with a finite clock skew, we propose a circuit technique to detect the worst Vmin in asynchronous clock operation. This circuitry allows us to screen the worst bit in an array that is conventionally obtained by a costly and time-consuming test procedure. For instance, we can at least realize 400x speed-up for the test time compared to the conventional method. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed experimentally that the worst Vmin can be successfully reproduced within 6% discrepancy by our proposed circuit.

A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues

We propose a circuit technique for an 8T dual-port (DP) SRAM in order to screen degraded minimum operating voltage (V min ) due to the write/read disturb issue. This circuitry allows us to generate the write/read disturb condition without relying on the conventional costly asynchronous operation. We designed and fabricated a 512-kb DP-SRAM macro using 28-nm low-power CMOS technology, and confirmed assured screening of failures in the write/read disturb operations.

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs

We discuss dynamic stability for single-port SRAM that manifests itself in the difference between minimum operating voltage (Vmin) for longer and shorter word-line (WL) pulse width (Twl). The most probable failure points (MPFPs) that determine Vmin for various Twl are investigated. Regarding dual-port SRAM, we identify the MPFP for the worst Vmin degraded by WL pulse skew between ports in asynchronous operation. The validity of our simulation results are verified through comparison with measured data for SRAM modules in 28 nm generation.

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline

We propose a partially write-assisted two read/write dual-port (DP) SRAM in 28-nm technology. Our write-assist circuit with metal-coupled capacitance can generate negative bitline bias which is flexibly adjustable to any bit-word configurations. By effectively applying assist biases only to sub-blocks with margin-less bits, power overhead can be reduced with Vmin improved. A test chip including proposed 512-kb DP SRAM macro is designed using 28-nm HKMG technology, from which we successfully observed 1-GHz operation at 1.0 V, 190 mV Vmin improvement, and 21% power reduction compared to a conventional assist.

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

With the rapid growth in the market for mobile information terminals such as smart phones and tablets, the performance of image processing engines (e.g., operation speed, accuracy in digital images) has improved remarkably. In these processors, 2-port SRAM (2P-SRAM) macros, in which a read port and a write port are operated synchronously in a single clock cycle, are widely used. Since the 2P-SRAM is placed in front of large scale logic circuitry for image processing, a faster access time (e.g., <;1 ns) is required. In general, the read-out operation in 2P-SRAM utilizes full-swing of the single read bitline (BL), so a drastic improvement of the access time is not expected. On the other hand, the dual-port SRAM (DP-SRAM) makes use of the voltage difference between BL pair in the read-out operation, which is suitable for the high-speed operation. In this study, we present a time-sharing scheme using a DP-SRAM cell to achieve high-speed access in 2P-SRAM macros in such image processors.

A Novel Low-Power and High-Speed SOI SRAM With Actively Body-Bias Controlled (ABC) Technology for Emerging Generations

An actively body-bias controlled (ABC) silicon-on-insulator (SOI) static random access memory (SRAM) connecting the bodies of the access and the driver transistors with the word line is proposed to realize high-speed and low-voltage operation. We developed the direct body contact to apply forward biases to the bodies without increases in the area penalty and the parasitic gate capacitance. An increase of the standby current does not occur because the body biases are not applied when the word-line voltage is low level. It is demonstrated that a significant speed improvement and a reduction of performance variations for the SRAM are achieved by applying the body bias. Neutron-accelerated soft-error tests reveal that the ABC structure suppresses soft-error events due to the body-tied SOI structure. In summary, the ABC SOI technology is one of the countermeasures for emerging generations.

40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU

A 160 kb SRAM macro with stable operation under widely various temperatures of -40 to 170°C is implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. We finely optimized MOS sizes of the 6T SRAM bitcell with process tuning to enhance the read margin and to reduce leakage power at high temperatures over 125°C. The optimized bitcell improves the static-noise-margin by 40 mV and reduces leakage power to 1/10 of the conventional value. To achieve high quality, we propose rush current suppression circuit when resuming from sleep-mode and a weak-bit test screening circuit. A designed test chip showed a measured Vmin mean of 0.65 V at 170°C and 1.86 μW/Mb (643 μW/Mb) at 25°C (170°C) with good distribution. Those are the lowest power values reported to date in published works. The estimated leakage power of a prototype MCU chip is acceptable for automotive target specifications.

2RW dual-port SRAM design challenges in advanced technology nodes

We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.

A 6.05-Mb/mm 2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time

High-density and low-leakage 1W1R 2-port (2P) SRAM is realized by 6T 1-port SRAM bitcell with double pumping internal clock in 16 nm FinFET technology. Proposed clock generator with address latch circuit enables robust timing design without sever setup/hold margin. We designed a 256 kb 1W1R 2P SRAM macro which achieves the highest density of 6.05 Mb/mm2. Measured data shows that a 313 ps of read-access-time is observed at 0.8 V. Standby leakage power in resume standby (RS) mode is reduced by 79% compared to the conventional dual-port SRAM without RS.