Miki Tanaka

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists

Scaling of process technology is inevitably accompanied by the increase of local variation in transistor characteristics, which has been deteriorating the operation margin of SRAM. This trend necessitates assist circuits for SRAM to increase the immunity against variations, and many papers in this area [1-4] have been published. In this paper, we present an assist circuit suitable for the SRAMs in 20nm generation. Figure 13.3.1 compares local variations of SRAM cell transistors, pass-gate NMOS (PG), pull-down NMOS (PD) and pull-up PMOS (PU) for 28 and 20nm, showing degradation as the process advances. Noticeably, the NMOS transistors become worse than PMOS, which causes degradation in SRAM operating margin since SRAM characteristics such as static noise margin (SNM) are more sensitive to NMOS than PMOS. Figure 13.3.1 also shows the operational window enclosed by read and write immunity against local variations in 28 and 20nm. This indicates assist circuits must perform beyond the level established in previously published work to address SRAM variation in advanced technology nodes. Lowering wordline (WL) voltage level is one of the read-assist approaches. Lowering the supply voltage of PU in a cell (ARVDD) and negative bitline (BL) techniques are known to be effective for the write operation. These techniques, however, have side-effects: lowering the WL voltage degrades write margin and lowering ARVDD leads to higher power consumption and a long cycle-time. Furthermore, the negative BL technique can cause write errors in non-selected columns. Thus, it is necessary to select which assist technique should be applied depending on each process technology. In addition, the SRAM used in production generally include single-port SRAM (SP-SRAM) and dual-port SRAM (DP-SRAM), so the assist circuits to be applied should be effective for whole SRAM family.

16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM macros with wordline overdriven assist

We demonstrate 16 nm FinFET High-k/Metal-gate SRAM macros with a wordline (WL) overdriven read/write-assist circuit. Test-chip measurements confirm improved minimum operating voltage (Vmin), standby leakage current, and access time compared to planar bulk CMOS. The proposed assist circuit improves Vmin by 50 mV and improves read-access-time by more than 1.5 times in 256-kbit SRAM macros. Read current (Iread) dependence against the fin diffusion length was observed. An extra design guard-band is needed to provide a reliable operation margin.

A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure

We developed a high density 1R/1W SRAM macro based on 8T-SRAM with an effective scheme for Design for Testability. To achieve a smaller Macro area, a differential sense amplifier is introduced to read the data, where the reference voltage for reading 0/1 data is generated by unselected cell array. In addition, we proposed a screening test circuit for read disturb operation. A 512 kbit two port SRAM macro based upon 28nm process was designed, confirming experimentally that the worst minimum operation voltage (Vmin) can be reproduced by our test circuit. The bit density of 3.16 Mb/mm2 was achieved, which is the highest among recent literatures.

2RW dual-port SRAM design challenges in advanced technology nodes

We examine appropriate bitcell layouts for two read/write (2RW) 8T dual-port (DP) SRAM in advanced planar/FinFET technologies. 256-kbit 2RW DP SRAM macros with highly symmetrical 8T DP bitcell were designed and fabricated using 16 nm FinFET technology. The read/write assist with wordline overdrive reduces Vmln by 120 mV, achieving successful operation at below 0.5 V.

A 6.05-Mb/mm 2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time

High-density and low-leakage 1W1R 2-port (2P) SRAM is realized by 6T 1-port SRAM bitcell with double pumping internal clock in 16 nm FinFET technology. Proposed clock generator with address latch circuit enables robust timing design without sever setup/hold margin. We designed a 256 kb 1W1R 2P SRAM macro which achieves the highest density of 6.05 Mb/mm2. Measured data shows that a 313 ps of read-access-time is observed at 0.8 V. Standby leakage power in resume standby (RS) mode is reduced by 79% compared to the conventional dual-port SRAM without RS.

1.8 Mbit/mm 2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology

A new bit-cell (BC) layout for ternary content-addressable memory (TCAM) is developed in a 16 nm Fin-FET process. The proposed BC is 15.8% smaller than the conventional BC. We design a 10kb TCAM macro which achieves the highest density of 1.8 Mbit/mm2. Measurement shows that total active power in our proposed macro is 8% less than that in the conventional one. A 484 ps of search access time is observed at 0.8 V, which marks the world fastest operation cycle of 1.25 G search per second at this time.

A dynamic/static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs

An embedded SRAM power management scheme using 16 nm FinFET technology is demonstrated in automotive infotainment SoCs. By introducing write-assist circuit technique, SRAM can operate down to 0.5 V wide voltage range, achieving DVFS for efficient power saving. Fast resume standby mode is also developed for reducing the leakage power of L1 cache under 2 GHz CPU operation. We confirmed that proposed thermal control scheme can be protected by thermal runaway failure.

Embedded SRAM designs for enhancing performance, power and area (PPA) in 16 nm FinFET technology

We demonstrate SRAM circuit design techniques for enhancing performance, power and area (PPA) in 16 nm FinFET technology. The wordline overdrive (WLOD) assist circuitries with dual power rail are introduced for not only 6T single-port SRAM bitcell but also for 8T dual-port bitcell, improving minimum operating voltage (Vmin) by enhancing write-abilities. The read access times are also improved by WLOD. We also implement a high-density 2-port SRAM using 6T bitcell with double pumping scheme, enabling about 2× higher density than conventional 8T bitcell design. The resume standby circuit, which is adoptively controlled the bias of VSS source lines in cell arrays, is introduced for reducing leakage power. The measured silicon data show that the Vmin, read access time, and standby power are improved by up to 45%, 50%, and 80%, respectively.

A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU

An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micro controller units (MCUs). The probing test step at low-temperature (LT) of -40°C is eliminated by imitating pseudo LT conditions in the final test step where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out with consideration of global and local Vt variations as well as contact soft open failure (high resistance), confirming good Vmin correlation between LT and pseudo LT conditions. Test chips with a 4-Mbit SRAM macro are designed and fabricated using 40-nm low-power CMOS technology. Measurement results show that the proposed test method can reproduce LT conditions and screen out low temperature failures with less overkill.