Malgorzata Kolopienczyk

Optimization Of Control Memory Size Of Control Unit With Codes Sharing

The method of design of compositional microprogram control unit with codes sharing is proposed. The proposed method is based on application of special address transformer to form an address of microinstruction on the base of its representation as pair code of operational linear chain, code of components. Such approach permits to use all positive features of codes sharing independently on characteristics of interpreted flow-chart of algorithm. The proposed method permits to decrease the size of control memory in comparison with all known methods of such control units design. An example of proposed method application is given

Time Dependencies Modelling in Traffic Control Algorithms

The paper presents the concept of discrete control systems for traffic control implementation on PLC devices. A transformation of popular finite state machine (FMS) model to the form that allows to represent the time dependencies is presented. An example of lights control on a pedestrian crossing is presented. Two implementation methods that can be a reference for particular real-life traffic control examples are discussed. Results of implementation of the example are shown.

Block Programming Technique in Traffic Control

In the paper there are discussed benefits of using the block-oriented approach in programming the PLC controller. As an example there is taken a model of traffic junction with multiple traffic flow (including the railway crossing). The model is described and control system structure is presented. There are discussed principles of block-oriented programming approach in Ladder Diagram (LAD) language. Benefits of using this technique are shown and example is discussed.

Optimization of Control Unit with Code Sharing

Abstract The method of design of compositional microprogram control unit with code sharing is proposed. The proposed method is based on application of special address transformer to form an address of microinstruction on the base of its representation as pair . Such approach permits to use all positive features of code sharing independently on characteristics of interpreted flowchart of algorithm, the optimal encoding of pseudoequivalent operational linear chains in particular. The proposed method permits to decrease the size of control memory in comparison with all known methods of such control units design. An example of proposed method application is given.

Hardware reduction for RAM-based Moore FSMs

A method is proposed allowing implementing logic circuit of Moore FSM with embedded memory block of FPGA chips. The method is based on replacement some part of the set of logical conditions by additional variables. It results in diminishing for the number of LUTs in the multiplexer used for replacement of logical conditions. An example of proposed design methods application is given.

Fault Detection Variants of the CloudBus Protocol for IoT Distributed Embedded Systems

Distributed embedded systems have become larger, more complex and complicated. More often, such systems operate accordingly to the IoT or Industry 4.0 concept. However, large number of ...

EMB - based design of Mealy FSM

Abstract A method is proposed allowing implementing Mealy FSM logic circuits with embedded memory blocks of FPGA chips. The method is based on transformation of FSM structure table and replacement of some logical conditions. Example of design and results of investigations are given.

Optimization of Control Memory Size of Control Unit with Codes Sharing

The method of design of compositional microprogram control unit with codes sharing is proposed. The proposed method is based on application of special address transformer to form an address of microinstruction on the base of its representation as pair <code of operational linear chain, code of components Such approach permits to use all positive features of codes sharing independently on characteristics of interpreted flow-chart of algorithm. The proposed method permits to decrease the size of control memory in comparison with all known methods of such control units design. An example of proposed method application is given.

CloudBus protocol hardware multi-converter gateway for distributed embedded systems

The CloudBus protocol is one of the methods which is used for data exchange and concurrent process synchronization in the distributed embedded systems. It realizes decentralized (distributed) control method, where each node is equal to each other. This communication model allows the significant savings in the amount of transmitted data between end modules. However, there are many distributed embedded systems, which are already implemented and working in the field. Switching the entire communication interface to the another protocol would result in high costs and process control interruption. This paper proposes a hardware converter which provides the integration of the CloudBus protocol with most popular protocols used in the industry. It allows for the extension and connection of the existing systems with the distributed embedded systems based on the CloudBus protocol. The research results provide performance and resource usage analysis for different converter architectures. The verification was performed on the SoC research and development platform for distributed embedded systems, which is based on Xilinx Zynq-7000.

Reducing hardware in FPGA-based Mealy FSM

This article is devoted to design of Mealy FSM with FPGAs using embedded memory blocks and look-up table elements. There is presented the state-of-the-art. The method is proposed for design of Mealy FSM logic circuit with embedded memory blocks based on encoding of collections of outputs and replacement of inputs. Example of design and research results are given.