Grzegorz Bazydlo

Translation UML diagrams into Verilog

The paper presents a method of using the UML state machine diagrams for specification of programs of logic controllers. The proposed method allows transformation from UML state machine diagram, using temporal Hierarchical Concurrent Finite State Machine (HCFSM) model, into Verilog hardware specification. The generated behavioral description in Hardware Description Language can afterwards be simulated, synthesized and implemented into e.g. FPGA device. A practical example illustrating the successive stages of the proposed method was also presented.

Dynamic Partial Reconfiguration of Concurrent Control Systems Implemented in FPGA Devices

A novel prototyping technique for concurrent control systems implemented in field programmable gate array (FPGA) devices is proposed in the paper. The method allows for dynamic modification of the implemented system. It means that the functionality of a part of the controller can be changed, while the rest of the system is still running. The approach applies to unified modeling language state machine diagrams as a specification of the system. Contrary to other methods, the presented concept requires neither major changes to the design, nor the application of external, specialized tools. The proposed idea has been experimentally verified with the use of Xilinx FPGAs.

Hardware realization of an SVM algorithm implemented in FPGAs

The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and “non-standard positions of control pulses” during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

Load shifting with the use of home energy management system implemented in FPGA

The increases for power demand in the Electrical Power System (EPS) causes a significant increase of power in daily load curve and transmission line overload. The large variability in energy consumption in EPS combined with unpredictable weather events can lead to a situation in which to save the stability of the EPS, the power limits must be introduced or even industrial customers in a given area have to be disconnected, which causes financial losses. Nowadays, a Transmission System Operator is looking for additional solutions to reduce peak power, because existing approaches (mainly building new intervention power unit or tariff programs) are not satisfactory due to the high cost of services in combination with insufficient power reduction effect. The paper presents an approach to load shifting with the use of home Energy Management System (EMS) installed at small end-users. The home energy management algorithm, executed by EMS controller, is modeled using Unified Modeling Language (UML). Then, the UML model is translated into Verilog description, and is finally implemented in the Field Programmable Gate Arrays. The advantages of the proposed approach are the relatively low cost of reduction service, small loss of end-users’ comfort, and the convenient maintenance of EMS. A practical example illustrating the proposed approach and calculation of potential gains from its implementation are also presented.

IoT security with one-time pad secure algorithm based on the double memory technique

Secure encryption of data in Internet of Things is especially important as many information is exchanged every day and the number of attack vectors on IoT elements still increases. In the paper a novel symmetric encryption method is proposed. The idea bases on the one-time pad technique. The proposed solution applies double memory concept to secure transmitted data. The presented algorithm is considered as a part of communication protocol and it has been initially validated against known security issues.

Design of EMB-Based Moore FSMs

The chapter deals with design of Moore FSMs based on using embedded memory blocks. The methods of trivial EMB-based implementation of logic circuits of Moore FSMs are discussed. In this case, only a single EMB is enough for implementing the logic circuit. Next, the optimization methods are discussed based on the structural decomposition leading to two-level models of FSMs. It is shown how to use the classes of PES for decreasing the number of EMBs in the final circuit. The last section considers different methods proposed for diminishing the hardware amount in LUTer implementing the block of replacement of logical conditions. It is shown that at least 17 different models can be used for optimizing the LUTer.

Dynamic partial reconfiguration of logic controllers implemented in FPGAs

Technological progress in recent years benefits in digital circuits containing millions of logic gates with the capability for reprogramming and reconfiguring. On the one hand it provides the unprecedented computational power, but on the other hand the modelled systems are becoming increasingly complex, hierarchical and concurrent. Therefore, abstract modelling supported by the Computer Aided Design tools becomes a very important task. Even the higher consumption of the basic electronic components seems to be acceptable because chip manufacturing costs tend to fall over the time. The paper presents a modelling approach for logic controllers with the use of Unified Modelling Language (UML). Thanks to the Model Driven Development approach, starting with a UML state machine model, through the construction of an intermediate Hierarchical Concurrent Finite State Machine model, a collection of Verilog files is created. The system description generated in hardware description language can be synthesized and implemented in reconfigurable devices, such as FPGAs. Modular specification of the prototyped controller permits for further dynamic partial reconfiguration of the prototyped system. The idea bases on the exchanging of the functionality of the already implemented controller without stopping of the FPGA device. It means, that a part (for example a single module) of the logic controller is replaced by other version (called context), while the rest of the system is still running. The method is illustrated by a practical example by an exemplary Home Area Network system.

Object Codes Transformation for Moore FSMs

This chapter deals with the original methods of hardware reduction based on the transformation of object codes of Moore FSMs. Two types of basic models of Moore FSMs with OCT are described, as well as EMB-based structures corresponding to these models. The design methods are proposed for the EMB-based FSMs with transformation of states into the collections of microoperations. Next, the design methods are shown allowing the transformation of the collections of microoperations into the states. The models of FSMs with the replacement of logical conditions and OCT are discussed. The additional hardware reduction is achieved due to using the classes of pseudoequivalent states.

Design of EMB-Based Mealy FSMs

This chapter deals with design of Mealy FSMs based on using embedded memory blocks. The methods of trivial EMB-based implementation of logic circuits of Mealy FSMs are discussed. In this case, only one EMB is enough for implementing the circuit. Next, the optimization methods are discussed based on encoding of the collections of microoperations and replacement of logical conditions. Also, the methods are discussed based on encoding of the rows of FSM structure table. All these methods lead to two-level models of Mealy FSMs. Next, these methods are combined together for further optimizing the hardware amount in FSM logic circuits. The last section considers different methods proposed for diminishing the hardware amount in LUTer implementing the block of replacement of logical conditions. The Chapter includes a lot of tables with results of investigations of proposed methods for the standard benchmarks.

Field Programmable Gate Arrays in FSM Design

The chapter is devoted to application of field programmable gate arrays (FPGA) in the design of logic circuits of FSMs. The general characteristic of FPGA is given. The methods are shown used for the trivial implementation (without the hardware reduction) of FSM’s logic circuits. The main methods of state assignment are discussed in details. At last, there are discussed the methods of hardware reduction for FPGA-based FSMs.