Kamil Mielcarek

Designing LUT-based mealy FSM with transformation of collections of output functions

A design method is proposed for LUT-based Mealy FSMs. The method is based on transformation of collections of output functions into state variables. Example of design and results of investigations are given. The method allows obtaining FSM logic circuits with less amount of LUTs than known from literature methods.

Designing Moore FSM with unstandard representation of state codes

A design method is proposed for FPGA-based Moore FSMs. The method is based on presentation of state codes as concatenations of codes of classes of pseudoequivalent states and collections of output functions. Examples of design and results of investigations are given. The method allows obtaining FSM logic circuits having less amount of LUTs than known from literature methods.

Design of FPGA-based Mealy FSMs with Counters

The article presents a novel method for diminishing the hardware amount in LUT-based Mealy FSMs. The method targets FSMs with state counters. It is based on replacement of FSM inputs by additional variables. To decrease the number of literals, the pairs of inputs are encoded. An example of synthesis is shown.

Hardware Reduction for Lut–Based Mealy FSMs

Abstract A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.

Designing Moore FSM with extended class codes

A method is proposed for designing LUT-based Moore FSMs. The method is based on splitting the set of classes of pseudoequivalent states. There are given example of design and results of investigations. The method allows obtaining FSM logic circuits having less amount of LUTs than known from literature methods.

Designing HFPGA-based Mealy FSMs with transformation of output functions

A design method is proposed for HFPGA-based Mealy FSMs. The method is based on transformation of collections of output functions into state variables. It allows diminishing the number of LUTs in FSM circuits in comparison with known method. There is an example of design shown in the article.

Designing Moore FSM with Transformation of State Codes.

A design method is proposed for FPGA-based Moore FSMs. The method is based on transformation of state codes into codes of collections of output functions and classes of pseudoequivalent states. Example of design and results of investigations are given.

Encoding of compatible micro-operations in LUT-based FSMs

This article shows a method of encoding of microoperations for LUT-based Mealy FSMs. The proposed design approach is based on two methods of structural decomposition of FSMs for diminishing the number of arguments for input memory functions in output functions. This method is viewed as an alternative to the encoding of collections of output functions. An example of design is given.

Reducing hardware in FPGA-based Mealy FSM

This article is devoted to design of Mealy FSM with FPGAs using embedded memory blocks and look-up table elements. There is presented the state-of-the-art. The method is proposed for design of Mealy FSM logic circuit with embedded memory blocks based on encoding of collections of outputs and replacement of inputs. Example of design and research results are given.

Design of EMB-Based Moore FSMs

The chapter deals with design of Moore FSMs based on using embedded memory blocks. The methods of trivial EMB-based implementation of logic circuits of Moore FSMs are discussed. In this case, only a single EMB is enough for implementing the logic circuit. Next, the optimization methods are discussed based on the structural decomposition leading to two-level models of FSMs. It is shown how to use the classes of PES for decreasing the number of EMBs in the final circuit. The last section considers different methods proposed for diminishing the hardware amount in LUTer implementing the block of replacement of logical conditions. It is shown that at least 17 different models can be used for optimizing the LUTer.