William J. Bright

Codec for echo-canceling, full-rate ADSL modems

A codec, fabricated in 3.3 V CMOS, provides the low-voltage transmitter and receiver interfaces between DSP and high voltage hybrid circuit for either the central office (CO) or the remote terminal (RT), configurable by metal mask option. The die area is 67.5 square millimeters. The power dissipation is 600 mW (CO) and 760 mW (RT).

A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC

Pipelined ADCs designed in analog BiCMOS technologies can offer good linearity and high SNR performance for input signals with reasonable voltage swings. Such ADCs, however, face two critical design challenges: the process limits the sampling rate, and the pipeline architecture limits power efficiency. This paper introduces a two-way time-interleaved (TI) switched-current 1Gs/s 12b pipelined ADC in SiGe BiCMOS that addresses these issues.

8 b 75 M sample/s 70 mW parallel pipelined ADC incorporating double sampling

This 8b pipelined analog-to-digital converter (ADC) incorporates double sampling into the residue signal path of a 1.5b-per-stage architecture to effectively double the throughput of the ADC for a given analog power consumption. Residue amplifiers and sub-ADC comparators are shared between two time-interleaved channels and the sampling capacitors in the second stage are scaled in order to reduce power consumption. The ADC presented here achieves 75 MSamples/s while consuming 70 mW. The converter measures 5.5 mm/sup 2/ and is fabricated in a 3.3 V 0.5 /spl mu/m digital CMOS process with four levels of metal and no special mask layers for passive components.

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC

This paper describes a 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T&H to improve the dynamic performance of the individual sub-ADCs and to reduce both the converter error rate and the complexity of the required interleaving background calibration algorithms. It achieves an SFDR of 79 dBc and 66 dBc at low and high frequency inputs, respectively and an error rate of less than 10-9, and has a power consumption of 1.15 W for the core ADC.

A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz

We show for the first time an 8.9 GS/s RF current-steering DAC, with an on-chip 1:1 Balun, and an 8-lane 12.5 Gbps JESD204B compliant SerDes, with a measured LTE ACPR >71 dBc in the adjacent 20 MHz band for a 2.9 GHz channel. The DAC has IM3 <;-65 dBc for output frequencies up to Nyquist. This performance is accomplished using a novel DAC switch driver and data/dummy-data scheme to minimize the pattern dependent sourcing/sinking of current on the DAC driver supply and ground. The DAC is fabricated in a 40nm dual-oxide CMOS process and dissipates 1.2W, with the contribution of the synthesized digital block and SerDes excluded.

Spatial averaging and ordering in matched element arrays

Spatial gradients often limit the matching accuracy of element arrays in ADCs and DACs. We cast. the problem of spatial gradients formally and present a global optimization-based solution that does not require the gradients to be pre-characterized precisely or limit them to being linear and/or quadratic. Si results from a standalone BiCMOS DAC and a CMOS DAC, part of the industrys first DOCSIS 1.1 certified cable modem solution, are presented.

A 12 bit 1.6 GS/s BiCMOS 2×2 hierarchical time-interleaved pipeline ADC

A 12 bit 1.6 GS/s pipeline ADC realized in a 0.18 μm complementary BiCMOS SiGe process is presented. The ADC consists of a four-way time-interleaved hierarchical structure and a master-slave T/H to improve the dynamic performance of the individual sub-ADCs and to reduce both the complexity of the required interleaving background calibration algorithms and the error rate. It achieves an SFDR of 79 dBc at low frequency inputs and 66 dBc at Nyquist, and has an error rate of less than 10-9.