Manash Chanda

Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow-power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on subthreshold adiabatic logic-based 4-bit CLA has also been addressed separately. Postlayout simulations show that subthreshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.

Analysis of noise margin of CMOS inverter in sub-threshold regime

In this paper, the Noise margin parameters of a CMOS inverter circuit in sub-threshold regime have been analyzed thoroughly with respect to variable supply voltage, transistor strength and temperature; without neglecting the significant DIBL and body bias effects. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points and logic threshold points. Extensive simulations have been done under 45 nm CMOS technology using CADENCE Spice spectra to ensure the correctness of the analysis.

Design and analysis of adiabatic complex sequential logic circuits in sub-threshold regime for ultra-low power application

This paper represents the energy efficient ultra low power adiabatic sequential logic circuits in sub-threshold regime for the first time in literature. Here, Efficient Charge Recovery Logic (ECRL) based on Differential Cascode Voltage Swing (DCVS) is adopted for the implementation of the circuits to achieve the ultra low power dissipation in sub-threshold regime. Single sinusoidal source is used as supply clock to enjoy the minimal power overheads. In this paper, adiabatic flip-flops and 8 bit Parallel - In - Serial - Out (PISO) shift register have been implemented in sub-threshold regime. Extensive CADENCE simulations for the first time in 22 nm technology node ensure that in sub-threshold regime, ECRL based flip-flops consume only 35% to 45% of total energy consumed by the static CMOS counterpart.

Design and implementation of adiabatic multiplier in sub-threshold regime for ultra low power application

This paper investigates the low power characteristics of transistor-based adiabatic ECRL logic styles in Sub-threshold regime for the first time in literature. Instead of the multiphase clocking, single clock source is used to enjoy the minimal power overheads. 4-2 Compressor has been implemented to validate the workability of the proposed logic in the sub-threshold regime. A vivid analysis of an 8×8 tree multiplier based on the above mentioned logic also has been implemented. The tree multiplier comprises three sub-circuits: a partial product generator, a partial product compression tree and finally a 16-bit carry look ahead adder. A uniform test bench is set up for fair comparison between the conventional CMOS based tree multiplier and ECRL based tree multiplier circuits to assure the advantage of the proposed logic in terms of power dissipation. Extensive CADENCE simulations have been done using 22nm technology file to analyze the effect of loading, temperature and the supply voltage on power dissipations of the proposed logic circuit design in sub-threshold regime.

Design and Analysis of a Logic Model for Ultra Low Power Near Threshold Adiabatic Computing

The behaviour of the adiabatic logic in the near threshold regime has been analysed in depth in this study. Near threshold adiabatic logic (NTAL) style can perform efficiently using a single sinusoidal power supply which reduces the clock tree management and enhances the energy saving capability. Power dissipation, voltage swing, effect of load, temperature, frequency etc. of NTAL circuits have been detailed here. Extensive CADENCE simulations have been done in 22 nm technology node to verify the efficacy of the proposed model. A power clock has been generated based on a switched capacitor regulator to drive the complex NTAL circuits. Analytical and simulated data match with high accuracy which validates the proposed adiabatic logic style in the near threshold regime. A significant amount of energy can be saved by the adiabatic logic with or without considering the power dissipation of the clock generator.

Adiabatic implementation of reversible architecture

Reversible logic has gained significant attention in ultra-low power computing. Adiabatic implementation of reversible gate, i.e., TOFFOLI gate has been analyzed in depth in this paper. Energy efficient single sinusoidal source has ensured the correct operation in the proposed reversible adiabatic architectures. Single sinusoidal source minimizes the clocking overhead and also ensures minimal control overhead and higher energy efficiency. Power dissipation issue is addressed in depth here. Extensive simulations show that adiabatic reversible gates consume very less power compared to the conventional static CMOS architectures. Such an approach is efficacious for the design of ultra-low power VLSI circuits where speed is not a pivotal issue, like Internet of Things (IoT), sensor node designs and portable applications.

Analysis of adiabatic ECRL NAND/NOR for ultra low power near-threshold computing

In this paper, the action of the adiabatic logic with proper sizing of aspect ratio has been inspected for the first time in literature for the requirement of ultra-low power applications. Hence, Efficient charge recovery logic (ECRL) is used as reference. Using single sinusoidal power supply, ECRL structure can execute efficiently which decreases the management of clock tree and increase capability of the energy saving. The required analytical expression of the current driven by PMOS, dissipated power, leakage energy dissipation, and maximum and minimum output voltages are detailed here. Substantial simulations have been carried out considering 22nm technology in near-threshold regime to analyze the behavior of adiabatic logic in near threshold regime. Significant energy saving can be achieved using the adiabatic structure over conventional structure in near threshold regime. Matching of simulated and analytical data with high caliber validates the suggested adiabatic logic structure in near threshold regime.

Comparative analysis of ultra-low power adiabatic logics in near-threshold regime

In this paper, a comparative study of transistor based various adiabatic logic styles has been done thoroughly for the first time in the near-threshold regime. A uniform simulation environment is taken into consideration for exact results. To verify the workability of the adiabatic logic styles in the near threshold regime, extensive simulations have been done considering 22nm technology. The study is based on the effect of the supply voltage, temperature, and capacitive load on power dissipations in various logic styles. Notable changes in consumption of power and degradation of output waveforms at different stages have been observed among the diverse set of logic styles chosen for analysis. From the simulation results Efficient Charge Recovery Logic (ECRL) is found to be most efficient in near-threshold regime and perform without sacrificing noise immunity and driving ability and consuming least power.

Analytical modelling of power dissipation and voltage swing of CMOS logic circuit for near-threshold computing

In near threshold computing (NTC), by aggressively scaling down the supply voltage to values near the threshold voltage, considerable reduction in power consumption and improvement in energy efficiency have been observed recently. In contrast to these advantages, there are problems like logic failures, performance variation that comes with NTC approach. Ambient temperature has been found to affect performance as well. In this paper, analytic expression of the power dissipation and the noise margin of a Inverter in near threshold regime have been done. Analysis of 1-bit, 4-bit, 8-bit and 16-bit Carry Look Ahead adders (CLAs) have been done in the near-threshold regime to show the workability of the near threshold logic circuits. Extensive CADENCE simulations have been done to verify the analytical modeling.

Design and analysis of adiabatic adder in near-Threshold regime for low power application

Adiabatic logic style is efficacious for the design and implementation of the low power, low performance digital system. As per our knowledge, till now no literature has been reported regarding the adiabatic logic for near threshold computing (NTC). This is the first time in literature, we would like to analyze the behavior of adiabatic logic circuits in near threshold regime for ultra-low power system implementation. Hence, we have observed the workability of the adiabatic adder in the near threshold regime to validate our proposal for the implementation of ultra low power digital system.