Swapnadip De

A new analytical subthreshold model of SRG MOSFET with analogue performance investigation

For the first time, a pseudo-two-dimensional (2D) approach is extended from a rectangular device structure to a cylindrical one. A pseudo-2D model applying Gausss law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in subthreshold regime is presented. From this pseudo-2D analysis, electrostatic potentials, current characteristics, the threshold voltage roll-off, the drain-induced barrier lowering and the subthreshold swing are explicitly modelled. The obtained analytical model has been extended to develop a model for transconductance-to-drain current ratio (g m/I d) in weak inversion regime. Analogue figures of merit of SRG MOSFETs are studied, including transconductance efficiency g m/I d, intrinsic gain and output resistance. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modelled expressions are compared with the simulated characteristics obtained from ATLAS device simulator.

Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed in depth for the first time in the literature to make great improvement in ultralow-power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns instead of performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The effect of temperature and process parameter variations on subthreshold adiabatic logic-based 4-bit CLA has also been addressed separately. Postlayout simulations show that subthreshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in 22-nm CMOS technology using CADENCE SPICE Spectra.

1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model

An analytical pseudo-two-dimensional (2-D) model for the transconductance generation factor ( g m /I d ) of cylindrical surrounding gate (SRG) metal-oxide-semiconductor field effect transistor (MOSFET) is presented. The model has been developed by applying Gausss law in the cylindrical channel depletion region for undoped or lightly doped silicon SRG MOSFET working in the subthreshold regime. In order to validate the model, the modelled expressions are compared with the simulated characteristics obtained from the numerical device simulator. A systematic investigation of analogue performance figures of merit are reported for different dimensions of SRG MOSFET. The obtained g m /I d model has been implemented in modelling the 1 /f low-frequency noise (LFN). The variation of 1/ f LFN is obtained and investigated for different device parameters.

Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs

This article presents an analytical surface potential, threshold voltage and drain current model for asymmetric pocket-implanted, single-halo dual material gate and double-halo dual material gate (DHDMG) n-MOSFET (MOSFET, metal–oxide–semiconductor field-effect transistor) operating up to 40 nm regime. The model is derived by applying Gausss law to a rectangular box, covering the entire depletion region. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends along with the inner fringing capacitances at both the source and the drain ends and the subthreshold drain and the substrate bias effect. Using the surface potential model, the threshold voltage and drain currents are estimated. The same model is used to find the characteristic parameters for dual-material gate (DMG) with halo implantations and double gate. The characteristic improvement is investigated. It is concluded that the DHDMG device structure exhibits better suppression of the short-channel effect (SCE) and the threshold voltage roll-off than DMG and double-gate MOSFET. The adequacy of the model is verified by comparing with two-dimensional device simulator DESSIS. A very good agreement of our model with DESSIS is obtained proving the validity of our model used in suppressing the SCEs.

Effect of fringing fields on subthreshold surface potential of channel engineered short channel MOSFETs

An analytical and accurate subthreshold surface potential model for short channel Conventional, LAC & double halo including the effect of inner fringing field is presented, considering the surface potential variation with the depth of the channel depletion layer. With this the drawback of existing models, the assumption of a constant channel depletion layer thickness is removed. A pseudo two dimensional method is adopted and we report a more accurate prediction of the surface potential including the fringing field effect.

Effect of fringing field in modeling of subthreshold surface potential in Dual Material Gate(DMG) MOSFETS

An analytical subthreshold surface potential model for Dual Material Gate MOSFET including the effect of inner fringing field is presented, considering surface potential variation with the depth of the channel depletion layer. A pseudo two dimensional method is adopted and a more accurate prediction of surface potential including the fringing field effect is reported.

Adiabatic implementation of reversible architecture

Reversible logic has gained significant attention in ultra-low power computing. Adiabatic implementation of reversible gate, i.e., TOFFOLI gate has been analyzed in depth in this paper. Energy efficient single sinusoidal source has ensured the correct operation in the proposed reversible adiabatic architectures. Single sinusoidal source minimizes the clocking overhead and also ensures minimal control overhead and higher energy efficiency. Power dissipation issue is addressed in depth here. Extensive simulations show that adiabatic reversible gates consume very less power compared to the conventional static CMOS architectures. Such an approach is efficacious for the design of ultra-low power VLSI circuits where speed is not a pivotal issue, like Internet of Things (IoT), sensor node designs and portable applications.

Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application

This paper shows that a conventional semi-custom design-flow based on a energy efficient adiabatic logic (EEAL) cell library allows any VLSI designer to design and verify complex adiabatic arithmetic units in a simple way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom EEAL-based 32-bit carry-lookahead adder (CLA) has been designed in a TSMC 90-nm CMOS process technology and verified by CADENCE Design suite. Differential cascode voltage swing (DCVS) logic has been used to implement the newly proposed EEAL and it uses only a sinusoidal clock supply to ensure correct operation. Post-layout simulations show that semi-custom adiabatic arithmetic units can save significant amount of energy, as compared to the previously reported single clocked adiabatic logic and logically equivalent static CMOS implementation. Extensive CADENCE simulations have been done for the verification of the functionality of the proposed logic structure.