Angsuman Sarkar

A new analytical subthreshold model of SRG MOSFET with analogue performance investigation

For the first time, a pseudo-two-dimensional (2D) approach is extended from a rectangular device structure to a cylindrical one. A pseudo-2D model applying Gausss law in the cylindrical channel depletion region for undoped or lightly doped surrounding gate (SRG) silicon metal oxide semiconductor field effect transistor (MOSFETs) working in subthreshold regime is presented. From this pseudo-2D analysis, electrostatic potentials, current characteristics, the threshold voltage roll-off, the drain-induced barrier lowering and the subthreshold swing are explicitly modelled. The obtained analytical model has been extended to develop a model for transconductance-to-drain current ratio (g m/I d) in weak inversion regime. Analogue figures of merit of SRG MOSFETs are studied, including transconductance efficiency g m/I d, intrinsic gain and output resistance. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modelled expressions are compared with the simulated characteristics obtained from ATLAS device simulator.

1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model

An analytical pseudo-two-dimensional (2-D) model for the transconductance generation factor ( g m /I d ) of cylindrical surrounding gate (SRG) metal-oxide-semiconductor field effect transistor (MOSFET) is presented. The model has been developed by applying Gausss law in the cylindrical channel depletion region for undoped or lightly doped silicon SRG MOSFET working in the subthreshold regime. In order to validate the model, the modelled expressions are compared with the simulated characteristics obtained from the numerical device simulator. A systematic investigation of analogue performance figures of merit are reported for different dimensions of SRG MOSFET. The obtained g m /I d model has been implemented in modelling the 1 /f low-frequency noise (LFN). The variation of 1/ f LFN is obtained and investigated for different device parameters.

RF and analogue performance investigation of DG tunnel FET

In this letter, the analogue and RF performance of a silicon double-gate tunnel FET (DGTFET) is reported. With the help of a device simulator, the variation of different analogue and RF device performance parameters are investigated, such as transconductance-to-drain-current ratio (gm/Id), intrinsic gain (gm/gds), cut-off frequency (fT), and maximum frequency of oscillation (fmax) as a function of channel length, are studied. Our results show that the reduction of channel length results in an improvement in the RF performance parameters of the device and deterioration of the analogue performance parameters of the device, clearly indicating a necessary design trade-off between the RF (bandwidth) and analogue performances (power efficiency). The investigation presented here exhibits a valuable result that the DGTFET devices with optimised gate length are suitable for low-power analogue and RF applications.

Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs

This article presents an analytical surface potential, threshold voltage and drain current model for asymmetric pocket-implanted, single-halo dual material gate and double-halo dual material gate (DHDMG) n-MOSFET (MOSFET, metal–oxide–semiconductor field-effect transistor) operating up to 40 nm regime. The model is derived by applying Gausss law to a rectangular box, covering the entire depletion region. The asymmetric pocket-implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends along with the inner fringing capacitances at both the source and the drain ends and the subthreshold drain and the substrate bias effect. Using the surface potential model, the threshold voltage and drain currents are estimated. The same model is used to find the characteristic parameters for dual-material gate (DMG) with halo implantations and double gate. The characteristic improvement is investigated. It is concluded that the DHDMG device structure exhibits better suppression of the short-channel effect (SCE) and the threshold voltage roll-off than DMG and double-gate MOSFET. The adequacy of the model is verified by comparing with two-dimensional device simulator DESSIS. A very good agreement of our model with DESSIS is obtained proving the validity of our model used in suppressing the SCEs.

Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET

In this article, the RF and analog performance of junctionless accumulation-mode bulk FinFETs is analyzed by employing the variation of fin width so that it can be used as a high-efficiency RF integrated circuit design. The RF/analog performance evaluation has been carried out using the ATLAS 3D device simulator in terms of evaluation of figure-of-merits metrics such as transconductance (gm), gate-to-source/drain capacitances (Cgg), cutoff frequency (fT), and maximum frequency of oscillation (fmax). Apart from RF/analog performance investigation, the variation of ON-current to OFF-current ratio (ION/IOFF) and transconductance generation factor (gm/Ids) have also been carried out. From this study, it is observed that smaller fin width of the device improves its performance.

Staggered Heterojunctions-Based Nanowire Tunneling Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications

This paper presents the analog/RF performance for an III–V semiconductor-based staggered hetero-tunnel-junction n-type nanowire (NW) tunneling field effect transistor (n-TFET), for the first time. The device parameters for analog/mixed-signaling applications, such as transconductance (gm), transconductance-to-drive current ratio (gm/IDS), output resistance (Rout), intrinsic gain and unity-gain cutoff frequency (fT) are studied for III–V based NW n-TFET, with the help of device simulator and compared with those for a similarly sized homojunction (HJ) NW n-TFET. The result reveals that the hetero-tunnel-junction n-TFETs outperform their HJ counterparts for analog/mixed-signal system-on-chip (SoC) applications.

Effect of fringing fields on subthreshold surface potential of channel engineered short channel MOSFETs

An analytical and accurate subthreshold surface potential model for short channel Conventional, LAC & double halo including the effect of inner fringing field is presented, considering the surface potential variation with the depth of the channel depletion layer. With this the drawback of existing models, the assumption of a constant channel depletion layer thickness is removed. A pseudo two dimensional method is adopted and we report a more accurate prediction of the surface potential including the fringing field effect.

Effect of fringing field in modeling of subthreshold surface potential in Dual Material Gate(DMG) MOSFETS

An analytical subthreshold surface potential model for Dual Material Gate MOSFET including the effect of inner fringing field is presented, considering surface potential variation with the depth of the channel depletion layer. A pseudo two dimensional method is adopted and a more accurate prediction of surface potential including the fringing field effect is reported.

Computing Surface Potential and Drain Current in Nanometric Double-Gate MOSFET Using Ortiz-Conde Model

Surface potential of lightly doped symmetric double-gate MOSFET is analytically evaluated using Ortiz-Conde model for different structural dimensions in nanometric range, and corresponding drain current is evaluated for lower region of applied bias. The device dimension is considered in nanometer range, and due to light doping, the result of potential distribution exhibits increasing nature with gate voltage, where potential drop across dielectric layer is taken into account for realistic calculation. Pinch-off voltage dependence on material and structural parameters is estimated from static characteristics, and corresponding drain resistance is calculated. Simulated findings are very close to the previously obtained results. Result will help to design DG for low power application.

Fast Squaring Technique for Radix Vicinity Numbers for Radix 2 n ± M with Reduced Computational Complexity

A fast squaring technique for the operands nearer to a particular radix is reported in this paper. The technique offers significantly less computational complexity which reduces the processing time to a large extent. Considering the applicability of the technique for a particular set of numbers which are in the vicinity of the corresponding radix, it is shown that the technique is equally acceptable for very large radix number. The proposed approach has been verified using Xilinx ISE Vertex-7 FPGA device. Simulated findings showed that with a significant increment in radix value (99.87%), the change of propagation delay is extremely small (2.33%), and corresponding increase in power dissipation is within tolerable range (29.84%). The results show the improvement in speed and computational complexity.