Manfred Ramin

CMOS Dual-Work-Function Engineering by Using Implanted Ni-FUSI

For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.

PMOSFET Reliability Study for Direct Silicon Bond (DSB) Hybrid Orientation Technology (HOT)

The use of hybrid orientation technology with direct silicon bond wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides exciting opportunities for easier migration of bulk CMOS designs to higher performance materials, particularly (110) Si for PMOSFETs for higher hole mobility. In this letter, a 3times mobility improvement and 36% drive current gain were achieved for PMOSFETs on (110) substrates. A systematic investigation of PMOSFET reliability was conducted, and significant degradation of negative bias temperature instability lifetime on (110) orientation was observed due to higher density of dangling bonds. We also report the crystal orientation dependence on ultrathin nitrided gate oxide time-dependent dielectric breakdown.

Amorphization and Templated Recrystallization (ATR) Study for Hybrid Orientation Technology (HOT) using Direct Silicon Bond (DSB) Substrates

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (110) crystal orientation layer bonded to a bulk (100) handle wafer provides promising opportunities for easier migration of bulk CMOS designs to higher performance materials. In this work, the integration of shallow-trench-isolation (STI) after amorphization and templated recrystallization (ATR) scheme for converting surface orientation from (110) to (100) was investigated. By optimizing the trade-off between ATR-induced triangular morphology and DSB layer thickness, a 3X holes mobility improvement and 36% drive current gain were achieved for PMOSFETs fabricated on (110) plane using DSB-HOT. In addition, un-loaded ring oscillators fabricated using DSB substrates show a 38% improvement compared with control CMOS on (100) wafers.

Junction Passivation for Direct Silicon Bond Hybrid Orientation Technology

Direct silicon bonding (DSB) for hybrid orientation technology has recently generated a lot of interest due to the significant performance enhancements reported for PMOS devices that are fabricated on alternative substrate orientations. Significantly higher leakage was observed for P+/N diodes if the junction depletion region was located close to the interface between the (110) and (100) Si surfaces. Hydrogen and fluorine passivation of this interface by ion implantation resulted in an order of magnitude improvement in the reverse leakage. In this brief, the experiments that performed using several dose levels of H2, F, and N implants are described. Electrical characterization data for reverse leakage, forward current, and ideality factors are presented in the form of cumulative probability plots, from which it is concluded that H and F passivation by ion implantation consistently provides a significant improvement in junction leakage, as compared to an unimplanted DSB wafer. An increase in the forward resistance was observed due to the implants, as compared to bulk Si (100) control samples.