Michael F. Pas

Effects of Drying Methods and Wettability of Silicon on the Formation of Water Marks in Semiconductor Processing

In-line observation and classification of water marks after the drying process was investigated with regard to the wettability of wafers and the drying methods applied. The formation of water marks was observed with a KLA wafer inspection system and a particle scanner on different hydrophilic and hydrophobic wafers with and without patterns. The wafers were spun and IPA vapor dried as a function of the air exposure time. The hydrophilic wafers did not create any water marks with either spin or vapor dries. The air exposure time and dry method are much more sensitive with the hydrophobic surfaces in creating water marks. The spin dry of hydrophobic wafers created a large quantity of water marks independent of the air exposure time. Homogeneously hydrophilic or hydrophobic wafers with and without patterns did not create any water marks following the vapor drying of wafers. However, the patterned wafers with both hydrophobic and hydrophilic sites created water marks even in IPA vapor dry. This indicates that the wettability and drying method of the wafer play an important role in creating water marks in semiconductor wet processes.

Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device. It can be used to refine the process/design in time so as to guarantee high production yield. In the case of migration of production of a specific device from a source fab to a target fab, yield estimation in the target fab can be accelerated by employing information from the source fab, assuming that the process parameter distributions in the two fabs are similar, but not necessarily the same. In this paper, we employ the Bayesian Model Fusion (BMF) technique for efficient yield prediction of a device in the target fab. BMF adopts prior knowledge from the source fab and combines it intelligently with information from a limited number of early silicon wafers from the target fab. Thus, BMF allows us to obtain quick and accurate yield estimates at the onset of production in the target fab. The proposed methodology is demonstrated on an industrial RF transceiver.

CMOS Dual-Work-Function Engineering by Using Implanted Ni-FUSI

For the first time, a simple CMOS fully silicided (FUSI) process achieving n/pMOS band-edge work function was demonstrated, which is fully compatible with conventional CMOS process. Dual-work-function CMOS FUSI, with a wide range of 800 mV, was achieved by implantation of Yb into the poly of the nMOS gate (4.1-eV work function) and Ga into the poly of the pMOS gate (4.9-eV work function), respectively. The placement of the tuning elements at the metal/dielectric interface was engineered with the thermal budget, as well as the implant dose and species.

Morphology and Integration of Rough Polycrystalline Silicon Films for DRAM Storage Cell Applications

This study evaluates the important aspects of deposition and integration of rough polycrystalline silicon films for dynamic random access memory (DRAM) storage capacitor applications. Electrical performance of rough polycrystalline films is investigated in terms of grain morphology and microstructural control. It is shown that the morphology, roughness, and doping of the films strongly affect the capacitor electrical performance. A strong correlation is observed between the surface roughness measured in terms of reflectance and the electrical area enhancement factor (AEF) of the films. Leakage current performance of rough and control/smooth electrode devices incorporating NO dielectric is evaluated. The results demonstrate that the leakage current density of the devices with rough electrode is less than the AEF times the leakage current density of the devices with control polysilicon electrode. Various integration approaches to fabricate the rough polysilicon storage electrode are examined. Lower thermal budget processing sequences are shown to be viable options. Rapid thermal based doping and dopant activation anneal processes are demonstrated as alternatives to high temperature furnace annealing sequences. Capacitance-voltage data is presented with AEF and dopant depletion analysis for devices incorporating lower thermal budget sequences. It is shown that phosphine gas-doping of the rough polysilicon electrode increases the AEF by 17% as a consequence of the doping process.

Full/partial depletion effects in FinFETs

Full/partial depletion effects are observed in n-channel FinFETs. Gate-induced floating body effect and degraded subthreshold slope are observed in partially depleted devices but not in fully depleted devices. Floating-body effects are observed in FD devices with applied negative back-gate bias.

Depth profiles of As and Sb angle‐implanted trenches measured by secondary ion mass spectrometry

Depth profiles of As and Sb angle‐implanted trench pilot wafers and a fully processed 16 MB dynamic random access memory chip have been measured using secondary ion mass spectrometry (SIMS) to determine the doping level in the walls of the trench capacitors. As and Sb exhibit similar behavior throughout the implant and analysis process. The SIMS data correlates well with scanning electron microscopy cross sections of the trenches and simple geometrical arguments as well as with capacitance‐voltage measurements of processed wafers. The presence of a gate dielectric does not appear to interfere with SIMS analysis of trench wall doping, and this technique is therefore applicable as a post‐process monitor of doping distribution.

Harnessing fabrication process signature for predicting yield across designs

Yield estimation is an indispensable piece of information at the onset of high-volume manufacturing (HVM) of a device. The increasing demand for faster time-to-market and for designs with growing quality requirements and complexity, requires a quick and successful yield estimation prior to HVM. Prior to commencing HVM, a few early silicon wafers are typically produced and subjected to thorough characterization. One of the objectives of such characterization is yield estimation with better accuracy than what pre-silicon Monte Carlo simulation may offer. In this work, we propose predicting yield of a device using information from a similar previous-generation device, which is manufactured in the same technology node and in the same fabrication facility. For this purpose, we rely on the Bayesian Model Fusion (BMF) technique. The effectiveness of the proposed methodology is evaluated using sizable industrial data from two RF devices in a 65nm technology.

Yield prognosis for fab-to-fab product migration

We investigate the utility of correlations between e-test and probe test measurements in predicting yield. Specifically, we first examine whether statistical methods can accurately predict parametric probe test yield as a function of e-test measurements within the same fab. Then, we investigate whether the e-test profile of a destination fab, in conjunction with the e-test and probe test profiles of a source fab, suffice for accurate yield prognosis during fab-to-fab product migration. Results using an industrial dataset of ~3.5M devices from a 65nm Texas Instruments RF transceiver design fabricated in two different fabs reveal that (i) within-fab yield prediction error is in the range of a few tenths of a percentile point, and (ii) fab-to-fab yield prediction error is in the range of half a percentile point.

Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device, as it can inform timely process and design refinements in order to achieve high yield, rapid ramp-up, and fast time-to-market. To date, yield estimation is generally performed through simulation-based methods. However, such methods are not only very time-consuming for certain circuit classes, but also limited by the accuracy of the statistical models provided in the process design kits (PDKs). In contrast, herein we introduce yield estimation solutions which rely exclusively on silicon measurements and we apply them toward predicting yield during: 1) production migration from one fabrication facility to another and 2) transition from one design generation to the next. These solutions are applicable to any circuit, regardless of PDK accuracy and transistor-level simulation complexity, and range from rather straightforward to more sophisticated ones, capable of leveraging additional sources of silicon data. Effectiveness of the proposed yield forecasting methods is evaluated using actual high-volume production data from two 65-nm RF transceiver devices.

Harnessing process variations for optimizing wafer-level probe-test flow

We propose a methodology for dynamically selecting an optimal probe-test flow which reduces test cost without jeopardizing test quality. The granularity of this decision is at the wafer-level and is made before the wafer reaches the probe station, based on an e-test signature which reflects how process variations have affected this particular wafer. The proposed method offers flexibility by optimizing test flow per process signature and its implementation is simple and compatible with most commonly used Automatic Test Equipment. Furthermore, unlike static test elimination approaches, whose agility is limited by the relative importance of the permanently dropped tests, the proposed method is capable of exploring test cost reduction solutions which achieve very low test escape rates. Decisions are made by an intelligent system which maps every point in the e-test signature space to the most appropriate probe-test flow. Training of the system seeks to optimize the test flow of each process signature in order to maximize test cost reduction for a given target of test escapes, thereby enabling exploration of the trade-off between test cost reduction and test quality. The proposed method is demonstrated on an industrial dataset of a million devices from a 65nm Texas Instruments RF transceiver.