Zhaoan Yu

A study of cycling induced degradation mechanisms in Si nanocrystal memory devices.

The endurance of Si nanocrystal memory devices under Fowler-Nordheim program and erase (P/E) cycling is investigated. Both threshold voltage (V(th)) and subthreshold swing (SS) degradation are observed when using a high program or erase voltage. The change of SS is found to be proportional to the shift of V(th), indicating that the generation of interface traps plays a dominant role. The charge pumping and the mid-gap voltage methods have been used to analyze endurance degradation both qualitatively and quantitatively. It is concluded that high erase voltage causes severe threshold voltage degradation by generating more interface traps and trapped oxide charges.

Improving resistance uniformity and endurance of resistive switching memory by accurately controlling the stress time of pulse program operation

In this letter, the impact of stress time of pulse program operation on the resistance uniformity and endurance of resistive random access memory (RRAM) is investigated. A width-adjusting pulse operation (WAPO) method which can accurately setup and measure switching time is proposed for improving the uniformity and endurance of RRAM. Different from the traditional single pulse operation (TSPO) method in which only one wide pulse is applied in each switching cycle, WAPO method utilizes a series of pulses with the width increased gradually until a set or reset switching process is completely finished and no excessive stress is produced. Our program/erase (P/E) method can exactly control the switching time and the final resistance and can significantly improve the uniformity, stability, and endurance of RRAM device. Improving resistance uniformity by WAPO compared with TSPO method is explained through the interdependence between resistance state and switching time. The endurance improvement by WAPO operation stems from the effective avoidance of the overstress-induced progressive-breakdown and even hard-breakdown to the conductive soft-breakdown path.

Unification of three multiphonon trap-assisted tunneling mechanisms

There are three basic multiphonon trap-assisted tunneling (TAT) mechanisms in the gate leakage current of a metal-oxide-semiconductor (MOS) structure: the short-ranged trap potential, nonadiabatic interaction and electric field induced trap-band transitions. In this paper, a comparison of these three mechanisms is made for the first time in a single (Schenk’s model) MOS structure. A properly box-normalized electron wave function in the SiO2 conduction band in an electric field is used to calculate the field ionization rate of a deep neutral trap. It is found that capture and emission rates of a deep neutral trap are almost the same in the short-ranged trap potential and nonadiabatic interaction induced TAT processes, so the two mechanisms give a similar contribution to the total TAT current. The calculated TAT current and the average relaxation energy (∼1.5 eV) due to these two mechanisms are in good agreement with the experimental results. In contrast, capture and emission rates in Schenk’s model are sev...

Impact of program/erase operation on the performances of oxide-based resistive switching memory

Further performance improvement is necessary for resistive random access memory (RRAM) to realize its commercialization. In this work, a novel pulse operation method is proposed to improve the performance of RRAM based on Ti/HfO2/Pt structure. In the DC voltage sweep of the RRAM device, the SET transition is abrupt under positive bias. If current sweep with positive bias is utilized in SET process, the SET switching will become gradual, so SET is current controlled. In the negative voltage sweep for RESET process, the change of current with applied voltage is gradual, so RESET is voltage controlled. Current sweep SET and voltage sweep RESET shows better controllability on the parameter variation. Considering the SET/RESET characteristics in DC sweep, in the corresponding pulse operation, the width and height of the pulse series can be adjusted to control the SET and RESET process, respectively. Our new method is different from the traditional pulse operation in which both the width and height of program/erase pulse are simply kept constant which would lead to unnecessary damage to the device. In our new method, in each program or erase operation, a series of pulses with the width/height gradually increased are made use of to fully finish the SET/RESET switching but no excessive stress is generated at the same time, so width/height-controlled accurate SET/RESET can be achieved. Through the operation, the uniformity and endurance of the RRAM device has been significantly improved.

Differential conductance as a promising approach for rapid DNA sequencing with nanopore-embedded electrodes

We propose an approach for nanopore-based DNA sequencing using characteristic transverse differential conductance. Molecular dynamics and electron transport simulations show that thetransverse diff ...

A Physical Model for the Statistics of the Set Switching Time of Resistive RAM Measured With the Width-Adjusting Pulse Operation Method

The correlation between the set time (t_set) and the initial off-state resistance (R_OFF) statistics for a Ti/ZrO₂/Pt bipolar resistive random access memory device was investigated. The width-adjusting pulse operation method, which can significantly improve the switching uniformity, was used to accurately measure t_set, and the gathered statistical data were analyzed using Weibull distributions. Both the Weibull slope (β_t) and the scale factor (t_set63%) of tset distributions were found to increase logarithmically with R_OFF. The observed t_set - R_OFF interdependence provides a guideline in improving the switching uniformity and optimizing the tradeoff between set speed and disturb immunity. An analytical cell-based model was developed to explain the R_OFF-dependent t_SET statistics, which can be implemented in statistical compact models and circuit simulators for improving RRAM cell design and memory performances.

A novel junction-assisted programming scheme for Si-nanocrystal memory devices with improved performance

A novel drain-junction-assisted hot electron programming scheme has been proposed for Si nanocrystal memory devices. Different from the conventional channel hot electron (CHE) injection, two electron injection paths are responsible for the proposed scheme. Experimental results show that the new scheme has a nearly 1 V memory window increase and almost 300 times faster programming speed rather than the conventional CHE method. Meanwhile, improved data retention and endurance characteristics have also been achieved with the enlarged memory window, which is mainly due to less tunnel oxide degradation during the program/erase cycling. Therefore, the new scheme is shown to be more promising for Si nanocrystal memory application.

The statistics of set time of oxide-based resistive switching memory

In this paper, the characteristics of the set time (t_set) correlated with the initial off-state resistance (R_off) were studied using a statistical method based on a Ti/ZrO₂/Pt RRAM device. The data were collected by the width-adjusting pulse operation (WAPO) method. The Weibull distribution is used to analyze t_set variation. Both the Weibull slope (β_t) and scale factor (t_set63%) of t_Set distributions increase logarithmically with R_off. An analytical cell-based model was developed to explain the experimental statistics. Our result provides an inspiration on the switching uniformity and optimization of the tradeoff between the set speed-disturb dilemma.

An simple approach to evaluate TID response in High Voltage MOSFET for 65nm flash technology

Two straightforward parameter extraction methods are proposed to characterize the main and parasitic transistors Total Ionizing Dose (TID) effect of High Voltage nMOSFET (HV-MOS) for 65nm flash technology. During radiation, the Vth and drain current of the main and parasitic transistor were extracted separately. Clear understanding of the impact of each transistors radiation response is helpful to optimize the design of radiation-hard flash memory.

Total ionizing dose effect investigated by in-situ measurements for a 65nm flash technology

In-situ measurement was introduced to characterize the total ionizing dose (TID) radiation response of high voltage (HV) nMOS devices and memory cells in a 65nm Flash technology. Device parameter shifts during both radiation and subsequent relaxation/annealing phases was monitored in real-time. For HV nMOS device, about 20% of the Vth shift and off state drain current (Ioff@Vg=0V) shift can recover after 1000sec post-radiation annealing. While the linear drain current (Idlin) exhibits monotonically decrease except for the initial radiation phase. In contrast, the flash cell Vth shift halts immediately after radiation stops, and the Vth keeps almost constant thereafter. The distinct difference of TID response behavior was attributed to different TID physical mechanisms of two types of devices. The work provides a new perspective for the short term TID response of Flash technologies.