S. K. Manhas

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the front-runner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22 -nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the ldquomore-than-Moorerdquo regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.

Analysis of MWCNT and Bundled SWCNT Interconnects: Impact on Crosstalk and Area

Multiwalled carbon nanotube (MWCNT) and bundled single-walled carbon nanotube (SWCNT) interconnect have provided potentially attractive solution in current deep submicrometer and nanoscale technology. This letter presents a comparative analysis between the MWCNT and the bundled SWCNT at different global interconnect lengths in terms of crosstalk-induced time delay and area by using a three-line-bus architecture. Each line of the bus architecture is replaced by the RLC models of the MWCNT and bundled-SWCNT interconnects. The crosstalk-induced time delay is predicted at the middle line (victim) when the other two lines (aggressors) are switched in the opposite direction. From HSPICE circuit simulation results, it has been observed that the overall improvement in the delay is 52.4% more for the MWCNT as compared with the equivalent bundled-SWCNT interconnects. Consequently, on an average, the MWCNT requires 97.8% lesser area as compared with the bundled-SWCNT interconnects for the same crosstalk-induced time delay.

Comparative study of drift region designs in RF LDMOSFETs

Systematic investigation of the drift region design of the RF LDMOSFET in terms of breakdown voltage, on-resistance, transconductance, capacitance and hot-carrier effects is presented. The incorporation of a source field plate allows for an increase of drift dose for a given breakdown voltage, which eases the tradeoff between the breakdown voltage and on-resistance, and the breakdown voltage and transconductance. However, the increased dose can significantly degrade hot-carrier reliability. A step-drift has enhanced hot-carrier immunity and lower capacitance, but, at the cost of increased on-state resistance and lower transconductance. Furthermore, a second origin of hot carriers is reported in the step-drift design, which may cause damage in the drift region. A deeper drift region design, which does not require an additional mask in comparison to the step-drift design, is investigated. The proposed approach shares all the advantages provided by the field plate design. Moreover, the lower concentration in the new drift region design leads to enhanced hot-carrier immunity.

Analysis of Delay and Dynamic Crosstalk in Bundled Carbon Nanotube Interconnects

Mixed carbon nanotube bundles (MCBs) are considered to be highly potential interconnect solutions in the current nanoscale regime. Different MCBs with random and spatial arrangements are proposed based on the placements of single- and multiwalled carbon nanotubes (CNTs) (SWNTs and MWNTs) in a bundle. Propagation delay and dynamic crosstalk performances are analyzed using the modified equivalent single conductor model of proposed MCB topologies. Encouragingly, a significant reduction in propagation delay and crosstalk delay is observed for a spatial arrangement of an MCB wherein MWNTs are placed peripherally to the centrally located SWNTs. Typically, the average delay with and without crosstalk is improved by 82.8% and 80%, respectively, compared to the MCB having randomly distributed SWNTs and MWNTs.

Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

In this letter, we investigate a novel vertical silicon nanowire-based (NW) complementary metal-oxide-semiconductor (CMOS) technology for logic applications. The performance and the behavior of two- and single-wire CMOS inverters are simulated and analyzed. We show that vertical NW based CMOS offers a reduction of up to 50% in layout area, along with delay reductions of 50% (two wire) and 30% (single wire) compared with fin-shaped field effect transistor (FinFET) technology. The results show that vertical NW CMOS technology has a very high potential for ultralow-power applications with a power saving of up to 75% and offers an excellent overall performance for deca-nanoscale CMOS.

Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis

In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMOS performance for 15 nm node. We find that the asymmetry in structure (between top and bottom electrodes) leads to asymmetric parasitic resistances and capacitances that play an important role in determining the circuit delays. Thus our models help to quantify the role of parasitics on VNW device and CMOS performance having device asymmetry. Further, these parasitic models have high potential for use in developing a compact model of a complete device for VNW circuit simulations.

Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform

In this letter, we investigate the effect of device and layout parasitics on circuit performance of vertical nanowire (VNW) CMOS technology. We evaluate the effect of source-drain extension (S/Dext) scaling and device asymmetry on device and circuit performances for 15 nm VNW CMOS. It is seen that, due to reduced series resistance, circuit delay continues to improve with S/Dext down to 10 nm, despite increased parasitic capacitances. Also, we show that asymmetry between top and bottom electrodes plays a strong role in determining circuit delay, while layout-dependent parasitics are of secondary importance. The results show that delay is increased by 65% with top electrode as source, which is attributed to increase in series resistance and gate-drain overlap capacitances. The comparison of VNW and FinFET CMOS shows nearly 40% delay reduction, highlighting excellent potential of VNW CMOS for 15 nm and below technology nodes.

Progress in silicon RF Power MOS technologies - current and future trends

In this paper, the current progress and factors limiting the performance of silicon RF Power device technologies are reviewed. Silicon VDMOSFETs have high linearity but the gain is low at frequencies in excess of 1 GHz. LDMOSFETs have higher gain and can operate up to 2.4 GHz. However, the linearity and reliability of LDMOSFETs is poor in comparison to VDMOSFETs. New architectures and evolving trends are discussed.

A Degradation Model of Double Gate and Gate-All-Around MOSFETs With Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers

The reliability of multigate metal-oxide-semiconductor (MOS) devices is an important issue for novel nanoscale complementary MOS (CMOS) technologies. We present an analytic degradation model of double-gate (DG) and gate-all-around (GAA) MOS field-effect transistors (MOSFETs) in the presence of localized interface charge. Furthermore, we consider the effect of channel mobile charge carriers that significantly enhances the accuracy of our model. In our model, an accurate definition of threshold voltage in terms of minimum channel carrier density is used. The proposed model accurately depicts the effect of hot-carrier-induced degradation (HCD) on the surface potential, threshold voltage, and subthreshold swing. The results show a good agreement with the technology computer-aided design (TCAD) SENTAURUS device simulator over a wide range of device parameters. The modeling results show that the HCD effect become more dominant for scaled-down DG/GAA MOSFET devices. A comparative HCD degradation analysis carried for DG and GAA MOSFETs to understand their reliability limits show that GAA has greater immunity to HCD than DG MOSFET. This highlights model accuracy and provides crucial insights for HCD-tolerant multigate MOSFET design.

Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances

FinFETs are poised to replace conventional MOSFETs at sub-22-nm technology nodes mainly due to their relatively planar compatible fabrication process. It is well known that FinFET device parasitics are critical for the propagation delay and power dissipation. However, a quantitative understanding of device parasitics for circuit design is yet to be attained. We report a new extension transistor-induced capacitance shielding (ETICS) phenomenon. In this phenomenon, the FinFET extension region forms a transistor, which shields gate-extension fringing field capacitance. Due to this phenomenon, we observe a strong dependence of effective values of FinFET logic gate capacitances on transition times of their terminal voltages, which is unlike the conventional transistors. We show that delay estimation methods need to be modified considering ETICS for efficient FinFET circuit design.