Marcin Kubica

Area-oriented technology mapping for LUT-based logic blocks

Abstract One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

Logic synthesis for FPGAs based on cutting of BDD

Abstract The paper presents theoretical background of a new concept of logic synthesis for LUT–based FPGAs. The idea of multi-output function description in the form of PMTBDD diagram is proposed. This form enables to carry out a simple analysis of multi-output function by appropriate algorithms which are dedicated to single-output functions. The essence of logic synthesis is searching for suitable PMTBDD cuttings. The choice of the PMTBDD cuttings enables to obtain an adequate decomposition path. As the result of BDD diagram cutting, SMTBDD diagrams are created. These diagrams are a generalized form of SBDD and MTBDD diagrams. The idea of choosing a cutting line, which matches LUTs included in FPGAs, is also proposed. The essence of the suggested method of searching for the best technology mapping is based on an analytical description of the efficiency of mapping. The experimental results, which prove efficiency of the proposed methods, are presented too.

Decomposition time effectiveness for various synthesis strategies dedicated to FPGA structures

The main goal of the paper is to compare the analyzed synthesis methods taking time effectiveness of the decomposition process into account. The basic difference between the compared methods is the function representation. Two of three analyzed synthesis algorithms (DekBDD and MultiDec) use function description in the form of BDD. In Decomp algorithm, which was the basis of developing DekBDD and MultiDec systems, the function was described in a table form. Thus, the paper includes the results of the experiments conducted for a set of benchmarks that indicate considerable advantage of decomposition algorithms in which the functions are represented in the form of BDD.

Strategy of logic synthesis using MTBDD dedicated to FPGA

Abstract The paper presents a synthesis strategy oriented to the implementation of multi-output functions into LUT-based FPGA. The key elements of the proposed method include the decomposition of multi-output functions and a technology mapping strategy. The essence of the proposed approach is based on searching for an appropriate decomposition path and the idea of cosharing logic resources. In the process of looking for cosharing logic resources, the algorithm which searches for equivalence classes plays a vital role, and is implemented on the basis of proposed modifications of BDD diagrams. The results obtained were compared with synthesis results from competitive methods.

Decomposition synthesis strategy directed to FPGA with special MTBDD representation

This paper presents the decompositional techniques to obtain partial logical resource sharing between logical structures associated with the respective single functions belonging to a multioutput function. In the case of the BDD function representation the decomposition is associated with the problem of single or multiple cutting diagram. In the paper, the authors focus on the problem of searching for functions for the joint implementation of the decomposition implemented by multiple cutting of SMTBDD diagrams. During the decomposition process the key is to develop effective methods of splitting and merging MTBDD diagrams. This problem was solved by introducing a new type of diagrams PMTBDD. The effectiveness of the developed methods has been confirmed experimentally.

Technology mapping based on modified graph of outputs

The paper focuses on the problem of technology mapping of multi-output function in PAL-based CPLDs. The graph of outputs is used in the process of technology mapping. The paper presents the method of the graph’s of outputs modification that makes the process of the synthesis more effective. The results of the experiments confirm efficiency of the proposed technique in comparison with the classical logic synthesis and technology mapping based on graph of outputs without modification.