Adam Opara

Decomposition-based logic synthesis for PAL-based CPLDs

Decomposition-based logic synthesis for PAL-based CPLDs The paper presents one concept of decomposition methods dedicated to PAL-based CPLDs. The proposed approach is an alternative to the classical one, which is based on two-level minimization of separate single-output functions. The key idea of the algorithm is to search for free blocks that could be implemented in PAL-based logic blocks containing a limited number of product terms. In order to better exploit the number of product terms, two-stage decomposition and BDD-based decomposition are to be used. In BDD-based decomposition methods, functions are represented by Reduced Ordered Binary Decision Diagrams (ROBDDs). The results of experiments prove that the proposed solution is more effective, in terms of the usage of programmable device resources, compared with the classical ones.

Logic synthesis strategy based on BDD decomposition and PAL-oriented optimization

A new strategy of logic synthesis for PAL-based CPLDs is presented in the paper. This approach consists of an original method of two-stage BDD-based decomposition and a two-level PAL-oriented optimization. The aim of the proposed approach is oriented towards balanced (speed/area) optimization. The first element of the strategy is original PAL-oriented decomposition. This decomposition consists in the sequential search for an input partition providing the feasibility for implementation of the free block in one PAL-based logic block containing a predefined number of product terms. The presented non-standard decomposition provides a means to minimize the area of the implemented circuit and to reduce of the necessary logic blocks in the programmable structure. The second element of the proposed logic synthesis strategy is oriented towards speed optimization. This optimization is based on utilizing tri-state buffers. Results of experiments prove that the presented synthesis strategy is especially effective for...

Logic synthesis for FPGAs based on cutting of BDD

Abstract The paper presents theoretical background of a new concept of logic synthesis for LUT–based FPGAs. The idea of multi-output function description in the form of PMTBDD diagram is proposed. This form enables to carry out a simple analysis of multi-output function by appropriate algorithms which are dedicated to single-output functions. The essence of logic synthesis is searching for suitable PMTBDD cuttings. The choice of the PMTBDD cuttings enables to obtain an adequate decomposition path. As the result of BDD diagram cutting, SMTBDD diagrams are created. These diagrams are a generalized form of SBDD and MTBDD diagrams. The idea of choosing a cutting line, which matches LUTs included in FPGAs, is also proposed. The essence of the suggested method of searching for the best technology mapping is based on an analytical description of the efficiency of mapping. The experimental results, which prove efficiency of the proposed methods, are presented too.

Decomposition time effectiveness for various synthesis strategies dedicated to FPGA structures

The main goal of the paper is to compare the analyzed synthesis methods taking time effectiveness of the decomposition process into account. The basic difference between the compared methods is the function representation. Two of three analyzed synthesis algorithms (DekBDD and MultiDec) use function description in the form of BDD. In Decomp algorithm, which was the basis of developing DekBDD and MultiDec systems, the function was described in a table form. Thus, the paper includes the results of the experiments conducted for a set of benchmarks that indicate considerable advantage of decomposition algorithms in which the functions are represented in the form of BDD.

Strategy of logic synthesis using MTBDD dedicated to FPGA

Abstract The paper presents a synthesis strategy oriented to the implementation of multi-output functions into LUT-based FPGA. The key elements of the proposed method include the decomposition of multi-output functions and a technology mapping strategy. The essence of the proposed approach is based on searching for an appropriate decomposition path and the idea of cosharing logic resources. In the process of looking for cosharing logic resources, the algorithm which searches for equivalence classes plays a vital role, and is implemented on the basis of proposed modifications of BDD diagrams. The results obtained were compared with synthesis results from competitive methods.

Decomposition synthesis strategy directed to FPGA with special MTBDD representation

This paper presents the decompositional techniques to obtain partial logical resource sharing between logical structures associated with the respective single functions belonging to a multioutput function. In the case of the BDD function representation the decomposition is associated with the problem of single or multiple cutting diagram. In the paper, the authors focus on the problem of searching for functions for the joint implementation of the decomposition implemented by multiple cutting of SMTBDD diagrams. During the decomposition process the key is to develop effective methods of splitting and merging MTBDD diagrams. This problem was solved by introducing a new type of diagrams PMTBDD. The effectiveness of the developed methods has been confirmed experimentally.