Marco Sosio

SAW-less analog front-end receivers for TDD and FDD

A multistandard SAW-less receiver is designed exploring a current-mode architecture. A class-AB common-gate transformer-based low-noise transconductor amplifier (LNTA) is used to provide high linearity and harmonic filtering. A resonant passive mixer is adopted in order to allow the current-mode operation and improve the harmonic rejection. A low-power divider with intrinsic 25% duty-cycle is introduced to drive the passive mixer. A second-order Rauch biquad with complex poles makes-up the IQ blocker tolerant baseband. The receiver is designed to be suitable for SAW-less TDD and typical FDD applications with 3.8 and 1.9 dB of NF and > 18 and > 16 dBm of IIP3, respectively, using only 32 mW for each receiver.

A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS

The design of RF integrated circuits, at the low voltage allowed by sub-scaled technologies, is particularly challenging in cellular phone applications where the received signal is surrounded by huge interferers, determining an extremely high dynamic range requirement. In-depth investigations of 1/f noise sources and second-order intermodulation distortion mechanisms in direct downconversion mixers have been carried out in the recent past. This paper proposes a fully integrated receiver front-end, including LNA and quadrature mixer, supplied at 750 mV, able to meet GSM specifications. In particular, the direct downconverter employs a feedback loop to minimize second-order common mode intermodulation distortion, generated by a pseudo-differential transconductor, adopted for minimum voltage drop. For maximum dynamic range, the commutating pair is set with an LC filter. Prototypes, realized in a 90-nm RF CMOS process, show the following performances: 51 dBm IIP2, minimum over 25 samples, 1 dB desensitization point due to 3-MHz blocker at -18 dBm, 3.5 dB noise figure (NF), integrated between 1 kHz-100 kHz, 15 kHz 1/f noise corner. The front-end IIP2 has also been characterized with the mixer feedback loop switched off, resulting in an average reduction of 18 dB.

A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS

Scaled CMOS proves to be suitable for the design of transceiver ICs at micro- and millimeter-waves. The effort is presently toward compact and low-power solutions in view of integrating several transceivers on the same chip enabling phased array systems. In this paper we present a 24 GHz receiver, based on a subharmonic direct conversion architecture, designed in a 65 nm node. The local oscillator takes advantage of the half frequency operation proving significantly lower power consumption when compared to conventional solutions running at received frequency. Stacked switches for subharmonic down-conversion are passive to save voltage room, current driven and loaded by a transresistance amplifier. Optimum biasing of the switches allows maximizing linearity while saving power in the baseband. The integrated LNA matching network is the bottleneck toward low sensitivities. The LNA design trades-off power consumption, gain and sensitivity. Detailed insights into implementation issues, critical in a single-ended topology where both forward and return signal paths have to be supported, are provided. The chip consumes 78 mW and occupies 1.4 mm2 of active area. Experiments show: 30.5 dB gain, 6.7 dB NF, -13 dBm IIP3.

A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC

A filtering ADC used to implement the complete base-band in a receiver chain is presented. Passive filtering and in-band noise shaping lead to a frequency dependent dynamic range that better fits with the system requirements of a wireless receiver. The 90nm CMOS prototype is embedded in a fully integrated tuner compliant with DVB-T and ATSC standards. For a 6MHz channel bandwidth, the filtering ADC exhibits a frequency dependent dynamic range varying from 75.6dB to 90dB while drawing 30mA from a 1.8V supply.

A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS

A direct-conversion front-end using a highly linear mixer is implemented in 90nm CMOS. The front-end shows 15kHz 1/f noise corner, 51dBm IIP2, 31.5dB gain, 3.5dB NF, and draws 15mA from 0.75 V

A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS

Performance of standard CMOS implementations has proved sufficient up to 60 GHz range and examples of operating blocks even beyond 60 GHz have been presented. Still, the choice of the receiver architecture entails several peculiar considerations in order to achieve a robust low-power solution. On the other hand, at high frequencies, to save power in both the VCO and dividers, it is desirable to synthesize a reference frequency that is lower than the received frequency. The authors have proposed a half-harmonic 24 GHz direct-conversion I/Q-receiver front-end with integrated multi-phase LO generation in 65 nm CMOS. Experiments show that adequate performance is achieved in a compact (2.1 mm2) low-power (below 100 mW) solution in an ultra- scaled RF CMOS process.

A 2G/3G Cellular Analog Baseband Based on a Filtering ADC

A current-driven low-pass filter embedded in a sigma-delta analog-to-digital converter is presented. The implementation of a class-B feedback digital-to-analog converter, together with in-band noise reduction and passive filtering, gives the possibility to handle challenging wireless communication scenarios with low power consumption. The architecture is a suitable candidate to implement the entire baseband analog section of a Global System for Mobile Communications-Universal Mobile Telecommunications System (GSM-UMTS) reconfigurable receiver.

A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers

The advent of wideband systems, e.g., software defined radios, cognitive radios and UWB technology, motivates research for new transceiver architectures and circuit topologies to arrive at compact and low power solutions. Reference frequency generation in wideband CMOS receivers is usually power and area hungry. In this paper a wide band quadrature demodulator, based on mixers reconfigurable between fundamental and sub-harmonic operation modes is presented. The technique allows covering an RF bandwidth three times larger than the frequency covered by the synthesizer. Multiple local oscillator phases are required for the proposed architecture. For low phase noise and fast settling time, they are generated by means of a multi-stage injection locked ring oscillator. This solution proves very accurate and power efficient and may find applications in other communication systems requiring multiple phase references. A demodulator test chip tailored to WiMedia UWB groups 1, 3, 4 (3.1-9.5 GHz), and comprising mixers and frequency synthesizer, has been realized in a 65 nm CMOS technology. Experimental results show 10 dB of conversion gain with 2.3 nV/sqrt(Hz) equivalent input noise voltage spectral density. IIP2 and IIP3, with interferers in the GSM and WLAN bands, are 40 dBm and 11 dBm respectively. The synthesizer displays maximum spurs level of -43 dBc, a state of the art phase noise of -128 dBc/Hz@10 MHz offset and a settling time of less than 6 ns with 43 m W only.

A CMOS Sub-Harmonic Architecture for Signal Down-Conversion at Ka-Band

Quadrature sub-harmonic mixing to DC or low-IF can be attractive for signal processing at Ka-band. Frequency translation is performed without the need for a local oscillator at the received signal frequency. A lower frequency reference takes advantage of the higher quality of tuning elements and avoids high frequency, power-hungry dividers in the synthesizer. Moreover DC offset and second-order inter-modulation distortion, due to poor LO-RF isolation, are mitigated by the LO running at lower frequency. This paper presents the receiver IC architecture and experiments from a quadrature demodulator realized in 65nm CMOS.

A reconfigurable demodulator with 3-to-5GHz agile synthesizer for 9-band WiMedia UWB in 65nm CMOS

Receiver ICs realized in CMOS technology leverage the narrowband nature of wireless standards to meet specifications at low power levels. The advent of wideband systems, e.g. software-defined radios and UWB technology, is determining new emphasis on innovative techniques for key RF circuit blocks, and on synthesizers in particular [1–4]. Ring-oscillator-based solutions lend themselves to wideband operation but the signal quality at moderate power consumption is usually inadequate, while LC-tank-based oscillators do not cover the range requiring multiple VCOs. Sum and difference frequencies can be generated from a single VCO and its divided replica by means of SSB mixers. Unfortunately, significant spurious tones are created due to non-idealities in the mixers. As an alternative, RF signals belonging to a wide frequency range can be demodulated in a single receiver chain by means of a downconverter, reconfigured between conventional and subharmonic operation modes. In this way, the local oscillator is required to cover only a fraction of the frequency range, demodulating the lower portion in conventional mode and the upper in subharmonic mode. For subharmonic downconversion, 4 differential phases of the same reference are needed but the advantage of the lower frequency range of operation outweighs the added complexity.