Marek Novotny

Finite element modeling of surface mount devices

The aim of this paper is to improve reliability of SMD connecting and to increase durability of these structures. 3D finite element analysis has been applied to determine the time-dependent solder joint fatigue response and under accelerated temperature cycling conditions (-40C to +125C, 15min ramps/15min dwells). And definition place with maximal stress value rising in solder joint under shearing. This paper describes recent developments made to the finite element modeling of SMD, extending its capability to handle viscoplastic behaviour. It also presents the validation of this approach and results obtained for an SMD. Lifetime predictions are made using the creep strain energy based models of Darveaux. This study discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool

Wire bonding power interconnection

This paper describes recent developments in the finite element modeling of wire bonding interconnection, extending its capability to handle viscoplastic behavior. In this project a test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards will be developed and realized. Especially the reliability of interconnections of semiconductor chips under high current regime until 10 A, or more, is emphasized. The aim of this paper is to improve the reliability of semiconductor chip power interconnection and to increase the durability of these structures. The first objective is to determine stress distribution in connection wires. Wire cracks may occur in places of maximal stress. Another objective is to investigate current distribution in wires. The theoretical results will be completed with data from real experiments.

Investigation of wire bonding power interconnection

This paper deals with the investigation of wire bonding power interconnection for standard CMOS chips, which is very important for power application. Base part of this research is the determination of power load by the wire. For testing are design two types of substrate, especially the FR4 and ceramic substrate. As a conductive thick film layer on the ceramic substrate is used two different pastes. First paste was AgPd and the second one AgPdPt. Various wire interconnections are made on each substrate. This contact are analyzing in term of power load. The evaluation of test is based on the value of power load, wire diameter, type of conductive layer on the substrate, etc.

Testing and simulation of wire bonding attach for higher current

The reliable semiconductor chips wire bonding is one of the basic steps for the receiving good quality of final electronic system as well suitable economical solution. This paper describes some results obtained during our research work concerning development of the test equipment for high current stress measurement, for standard CMOS technology. High current density and high temperature gradient, which evoke in electronic devices the thermo mechanical stress, are the major reliability concerns for the future generation of high density power electronics. The developed Multi Channel High Current Test System is a PC based, stand alone driver and measurement tool, which is intended for the above described reliability testing. The equipment is able to measure small changes in connection resistance during long term reliability tests, where the contact is stressed by current up to 10 A. For this purpose was designed and realized in AMIS CMOS 0.7 technology semiconductor test chip (Fig. 1) that enable to measure maximum charge of current for different types of wires and served for study of chip pads degradation during increasing current load. The chip that includes heating resistor for simulation of temperature conditions was mounted on both, organic (FR-4) and inorganic (alumina) substrate to investigate chip pads degradation. Wire bonding was performed with different Al wire diameters (25µm, 50µm, 150µm and 300 µm, as well ribbon 150 × 13µm) and current capacity was investigated. Currently with this experimental work the modeling and simulation of electrical (current density and potential distribution) and thermo mechanical stressing were implemented. There was applied ANSYS to make the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. The first object was determining the stress distribution in connection wires because the most probably crack of the wire is in the place with the maximal stress value. Next object is the investigation of the current distribution in wires. The theoretical results are compared with test data of real experiment. The final aim of this paper is to show how to assure reliability of semiconductor chip for power interconnection and how to increase durability of these structures in the practical use. This paper describes some results achieved in the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. A test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards is focused on investigation of interconnection reliability for semiconductor chips under high current regime until 10 A, or more.

Virtual laboratory of microelectronic technologies

The paper deals with virtual laboratory module developed within educational process at Department of Microelectronics, FEEC, BUT. The virtual laboratory is intended for both fulltime and distance study, and the public. The lab serves as subsidiary learning tool, briefly describes existing microelectronic technologies and shows how they work. The work is focused on enhancement of students and the public interest about microelectronic technologies.

Measurement Environment for Reliability Study of High Current First Level Interconnections

Reliability of integrated circuits in electronic packages and connections is a major concern, due to the increasing die size, power dissipation and temperature. The extension of existing interconnection technologies towards higher current/power handling capabilities is a challenging and demanding task. In this paper a powerful system for experimental evaluation and reliability study for high current first level interconnections, up to 20 A, is presented. The system is used for evaluation of wire and flip-chip interconnections.

Reliability of solar cell's solder joints

This work is about interconnection of the solar cell and the substrate. Ceramic substrate and back side contact solar cells were used. There are 36 solar cells which were contacted on 12 substrates. The Ag paste was used as a conductive layer and lead free solder paste was chosen as a solder. 3 firing profiles in 4-zone furnace were tested. The thermal cycling is the next step. 6 substrates will be tested with 1000 cycles and 6 substrates will be tested with 3000 cycles. The cycle is in the range -40degC to 125degC, ramp 10degC/min, dwell 10 min, period 60 min. This is the common test cycle regime used in military applications testing, hence the wide temperature range of the cycle.

Comparing of simulation and experimental results of chip power interconnection

This paper describes recent developments made to the finite element modeling of wire bonding interconnection, extending its capability to handle viscoplastic behavior. In this project a test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards will be developed and realized. Especially the reliability of interconnections of semiconductor chips under high current regime until 10 A, or more, is emphasized.

Impact of solder pad shape on lead-free solder joint reliability

This paper deals with hand lead-free soldering process optimization. The work is focused on the impact of solder pads shape in combination with solder pads finish on lead-free solder joints reliability.

Chip Power Interconnection

This paper describes recent developments made to the finite element modeling of wire bonding interconnection, extending its capability to handle viscoplastic behavior. In this project a test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards will be developed and realised. Especially the reliability of interconnections of semiconductor chips under high current regime until 10 A, or more, is emphasised. This study discusses the analysis methodologies as implemented in the ANSYS finite element simulation software tool. The aim of this paper is to improve reliability of chip interconnection and to increase durability of these structures.