Martin Bursik

Some remarks to the effectiveness of the cleaning in electronics production process

This paper deals with research of the cleaning methods efficiency measurement in the sector of electronics assembly technologies. The cleaning is a necessary technological step whose importance is increasing with the development towards smaller resolution. Increased miniaturization, higher speeds and tighter board space highlights that need, as well as request for a higher reliability in some types of applications (automotive, medical, military etc.). Moreover, with introduction of new environmental regulations (WEEE, RoHS) and eco-design (EuP) rules the cleaning becomes to be more and more in the centre of attention. The cleaning process is important for various parts of technological processes, including lead-free solders process. Any various contaminants such as ionic or non-ionic flux residues, etching residues, handling contamination, fingerprints etc. can cause a decrease of lifetime could reduce lifetime and cause fatal failures. Therefore cleanliness is only the only way how to achieve acceptable reliability of electronic circuits and assemblies. But there is not enough information on which method to choose and how to arrange parameters. Described in this paper is the new method for measurement of cleaning efficiency by optical valuation, and some obtained results are discussed.

Investigation of wire bonding power interconnection

This paper deals with the investigation of wire bonding power interconnection for standard CMOS chips, which is very important for power application. Base part of this research is the determination of power load by the wire. For testing are design two types of substrate, especially the FR4 and ceramic substrate. As a conductive thick film layer on the ceramic substrate is used two different pastes. First paste was AgPd and the second one AgPdPt. Various wire interconnections are made on each substrate. This contact are analyzing in term of power load. The evaluation of test is based on the value of power load, wire diameter, type of conductive layer on the substrate, etc.

Evaluation of cleaning in electronics production process

Cleaning processes used in electronics productions are limited by cleaning efficiency. Those according to physical principle particular cleaning processes limits the area of application of existing system. At the selection of cleaning equipment is very important specification of their efficiency. For this purpose we have developed the quantifiable analyze of contaminated patterns. Evaluating is realized by test pattern on which are applied cleaning processes with different parameters. Next operation is visual controlling of residual contamination. In this way we are capable to determinate the average efficiency of cleaning system, specific efficiency on concrete test pattern and the homogeneity of cleaning efficiency in cleaning chamber. Important for cleaning process is an activity of cleaning medium. The activity of cleaning medium must be over minimum limits. Time intervals are set constant by the parameters of cleaning process especially its activity. For this reason is useful online monitoring of cleaning medium efficiency. This method requires universal sensor of medium activity.

Testing and simulation of wire bonding attach for higher current

The reliable semiconductor chips wire bonding is one of the basic steps for the receiving good quality of final electronic system as well suitable economical solution. This paper describes some results obtained during our research work concerning development of the test equipment for high current stress measurement, for standard CMOS technology. High current density and high temperature gradient, which evoke in electronic devices the thermo mechanical stress, are the major reliability concerns for the future generation of high density power electronics. The developed Multi Channel High Current Test System is a PC based, stand alone driver and measurement tool, which is intended for the above described reliability testing. The equipment is able to measure small changes in connection resistance during long term reliability tests, where the contact is stressed by current up to 10 A. For this purpose was designed and realized in AMIS CMOS 0.7 technology semiconductor test chip (Fig. 1) that enable to measure maximum charge of current for different types of wires and served for study of chip pads degradation during increasing current load. The chip that includes heating resistor for simulation of temperature conditions was mounted on both, organic (FR-4) and inorganic (alumina) substrate to investigate chip pads degradation. Wire bonding was performed with different Al wire diameters (25µm, 50µm, 150µm and 300 µm, as well ribbon 150 × 13µm) and current capacity was investigated. Currently with this experimental work the modeling and simulation of electrical (current density and potential distribution) and thermo mechanical stressing were implemented. There was applied ANSYS to make the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. The first object was determining the stress distribution in connection wires because the most probably crack of the wire is in the place with the maximal stress value. Next object is the investigation of the current distribution in wires. The theoretical results are compared with test data of real experiment. The final aim of this paper is to show how to assure reliability of semiconductor chip for power interconnection and how to increase durability of these structures in the practical use. This paper describes some results achieved in the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. A test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards is focused on investigation of interconnection reliability for semiconductor chips under high current regime until 10 A, or more.

New facts from lead-free solders reliability investigation

The lead-free soldering, required by RoHS legislative, has brought many new factors in the solder process as well in reliability and longevity of solder joints, which occur in high quantity in most electronic equipments and systems. In this paper is described a part of the research work, which runs at Brno University of Technology. The aim is to investigate some factors which influencing solder joint reliability and voids restriction, especially by reflow soldering process. The core factor for prediction and evaluation of solder joint reliability is solder joint structure that was monitored on scanning microscope for different solder compositions and processes, where some results were published last year [1]. Our experimental work has indicated that the solder joint structure is strong affected by temperature profile during reflow soldering, especially by speed of the cooling. That is why we have prepared special equipment for cooling to target this parameter for different types of solder materials. Obtained results have shown that the cooling phase has significant effect on solder joint structure formation, especially on creation and forming of intermetalic compounds. That means the cooling phase of the temperature reflow profile has to be setup very carefully to avoid problems with solder joint reliability. Further, we have been leaded new research work to influence the creating of solder joint structure by delivery of supplementary energy in reflow soldering process. First results have shown it could be other way, how to arrange and control better reflow process to assure higher reproducibility and quality of solder joints. Additionally we have tested patterns after thermal cycling by shear test. To make good comparison we studied together with SnPb alloy also SnAgCu (SnAg) and SnCuNiGe system.

Innovation in microelectronics technology education

This paper deals with presentation of some new aspects in study program of Microelectronics Technology on Faculty of Electrical Engineering and Communication Technology at Brno University of Technology. Microelectronics technology education makes a part of new study program that there was introduced in last years. This study program consists from three levels, Bachelor, Master and Doctorate degree. Subjects concerning Microelectronics technology make the fix part of this program and they are more and more popular among students from reasons concerning the practical education process. This fact is based on some new teaching activities that were incorporated in curriculum of both, bachelor and master subjects as shown in this paper.

Optimizing the cleaning process through cleaning efficiency examination

The paper explores the efficiency of cleaning methods in order to select a method and optimize cleaning as a part of assembly manufacturing process in microelectronics. To find out the advantages and potentialities of each single cleaning method it is necessary to use simple but reliable evaluation method. In this paper are under consideration two different methods for contamination evaluation, the first being the standard one using the contaminometer, and the second, new one, which is developed on an optical principle. The new method for cleaning evaluation is based on measuring the contamination in special substrate pattern using a scanning unit (programmable automated optical inspection). The special pattern was designed and realized on a glass substrate with ceramic chip models. The experimental part presents the efficiency examination and compares ultrasonic cleaning in microemulsion to other methods like spray in the air etc. The results of this study are used in optimizing and adjusting cleaning equipments as well as in their improvement and innovation.

System for maintaining the dispensing capillary at a constant height above the surface

This article describes a system for maintaining the dispensing capillary at a constant height above the surface of the substrate. Used substrates are not sufficiently planar and it is therefore necessary to correct the height of the capillary during dispensing process (constant height with +/- 5 μm tolerance above substrate is necessary). Non-planarity of substrates is typically 150 microns over the entire surface.

Innovative procedures for the evaluation method of the efficiency in the cleaning process

High-quality electronic assemblies, especially with “Fine Pitch” components, frequently need an effective but nonetheless environmentally friendly cleaning process. This paper deals with the development of an evaluation method of cleaning processes in microelectronics assembly technology. The elaboration of optimum parameters of the cleaning process for individual applications and the cleaning process efficiency as well as an innovative methodology based on the use of patented test substrates is in detail described in this paper.

New method for adjustment of elevation of the ceramic flatness for direct deposition

This paper deals with dispensing technology process, some times known “writing”, regarding high resolution deposition of thixotropic materials including standard conductor, resistor and dielectric thick film pastes with common viscosity values. The aim of this work is to achieve in the reproducible process the resolution below 100 μm. In this case, it is necessary to use a higher level of the optimization in comparison with standard conditions. Dispensing system for high resolution printing as a whole is to be divided into several categories. It is necessary to start from the preparation of the substrate and his elevation fixation with dispensing head. Due to the fact that the commercial supplied ceramic substrate for hybrid integrated circuits (usually alumina) does not meet the required geometric parameters for high precision printing inevitable to make a correction for curvature of the surface. While during the printing with common resolution 500 μm is not affected by the flatness of the ceramic surface, in the case of resolutions better than 200 μm (<; 100 μm) are subtle motifs practically impossible to print. To assure constant distance between ceramic surface and the dispensing unit is necessary to control Z axis level of the dispensing unit in conformity with corresponding actual value. This fact results from thixotropic materials physical behavior during the dispensing process, where distance fluctuation has to be smaller than 10 μm [1,2,3].