Jaroslav Jankovsky

Wire bonding power interconnection

This paper describes recent developments in the finite element modeling of wire bonding interconnection, extending its capability to handle viscoplastic behavior. In this project a test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards will be developed and realized. Especially the reliability of interconnections of semiconductor chips under high current regime until 10 A, or more, is emphasized. The aim of this paper is to improve the reliability of semiconductor chip power interconnection and to increase the durability of these structures. The first objective is to determine stress distribution in connection wires. Wire cracks may occur in places of maximal stress. Another objective is to investigate current distribution in wires. The theoretical results will be completed with data from real experiments.

Investigation of wire bonding power interconnection

This paper deals with the investigation of wire bonding power interconnection for standard CMOS chips, which is very important for power application. Base part of this research is the determination of power load by the wire. For testing are design two types of substrate, especially the FR4 and ceramic substrate. As a conductive thick film layer on the ceramic substrate is used two different pastes. First paste was AgPd and the second one AgPdPt. Various wire interconnections are made on each substrate. This contact are analyzing in term of power load. The evaluation of test is based on the value of power load, wire diameter, type of conductive layer on the substrate, etc.

Testing and simulation of wire bonding attach for higher current

The reliable semiconductor chips wire bonding is one of the basic steps for the receiving good quality of final electronic system as well suitable economical solution. This paper describes some results obtained during our research work concerning development of the test equipment for high current stress measurement, for standard CMOS technology. High current density and high temperature gradient, which evoke in electronic devices the thermo mechanical stress, are the major reliability concerns for the future generation of high density power electronics. The developed Multi Channel High Current Test System is a PC based, stand alone driver and measurement tool, which is intended for the above described reliability testing. The equipment is able to measure small changes in connection resistance during long term reliability tests, where the contact is stressed by current up to 10 A. For this purpose was designed and realized in AMIS CMOS 0.7 technology semiconductor test chip (Fig. 1) that enable to measure maximum charge of current for different types of wires and served for study of chip pads degradation during increasing current load. The chip that includes heating resistor for simulation of temperature conditions was mounted on both, organic (FR-4) and inorganic (alumina) substrate to investigate chip pads degradation. Wire bonding was performed with different Al wire diameters (25µm, 50µm, 150µm and 300 µm, as well ribbon 150 × 13µm) and current capacity was investigated. Currently with this experimental work the modeling and simulation of electrical (current density and potential distribution) and thermo mechanical stressing were implemented. There was applied ANSYS to make the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. The first object was determining the stress distribution in connection wires because the most probably crack of the wire is in the place with the maximal stress value. Next object is the investigation of the current distribution in wires. The theoretical results are compared with test data of real experiment. The final aim of this paper is to show how to assure reliability of semiconductor chip for power interconnection and how to increase durability of these structures in the practical use. This paper describes some results achieved in the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. A test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards is focused on investigation of interconnection reliability for semiconductor chips under high current regime until 10 A, or more.

New facts from lead-free solders reliability investigation

The lead-free soldering, required by RoHS legislative, has brought many new factors in the solder process as well in reliability and longevity of solder joints, which occur in high quantity in most electronic equipments and systems. In this paper is described a part of the research work, which runs at Brno University of Technology. The aim is to investigate some factors which influencing solder joint reliability and voids restriction, especially by reflow soldering process. The core factor for prediction and evaluation of solder joint reliability is solder joint structure that was monitored on scanning microscope for different solder compositions and processes, where some results were published last year [1]. Our experimental work has indicated that the solder joint structure is strong affected by temperature profile during reflow soldering, especially by speed of the cooling. That is why we have prepared special equipment for cooling to target this parameter for different types of solder materials. Obtained results have shown that the cooling phase has significant effect on solder joint structure formation, especially on creation and forming of intermetalic compounds. That means the cooling phase of the temperature reflow profile has to be setup very carefully to avoid problems with solder joint reliability. Further, we have been leaded new research work to influence the creating of solder joint structure by delivery of supplementary energy in reflow soldering process. First results have shown it could be other way, how to arrange and control better reflow process to assure higher reproducibility and quality of solder joints. Additionally we have tested patterns after thermal cycling by shear test. To make good comparison we studied together with SnPb alloy also SnAgCu (SnAg) and SnCuNiGe system.

System for maintaining the dispensing capillary at a constant height above the surface

This article describes a system for maintaining the dispensing capillary at a constant height above the surface of the substrate. Used substrates are not sufficiently planar and it is therefore necessary to correct the height of the capillary during dispensing process (constant height with +/- 5 μm tolerance above substrate is necessary). Non-planarity of substrates is typically 150 microns over the entire surface.

Innovative procedures for the evaluation method of the efficiency in the cleaning process

High-quality electronic assemblies, especially with “Fine Pitch” components, frequently need an effective but nonetheless environmentally friendly cleaning process. This paper deals with the development of an evaluation method of cleaning processes in microelectronics assembly technology. The elaboration of optimum parameters of the cleaning process for individual applications and the cleaning process efficiency as well as an innovative methodology based on the use of patented test substrates is in detail described in this paper.

New method for adjustment of elevation of the ceramic flatness for direct deposition

This paper deals with dispensing technology process, some times known “writing”, regarding high resolution deposition of thixotropic materials including standard conductor, resistor and dielectric thick film pastes with common viscosity values. The aim of this work is to achieve in the reproducible process the resolution below 100 μm. In this case, it is necessary to use a higher level of the optimization in comparison with standard conditions. Dispensing system for high resolution printing as a whole is to be divided into several categories. It is necessary to start from the preparation of the substrate and his elevation fixation with dispensing head. Due to the fact that the commercial supplied ceramic substrate for hybrid integrated circuits (usually alumina) does not meet the required geometric parameters for high precision printing inevitable to make a correction for curvature of the surface. While during the printing with common resolution 500 μm is not affected by the flatness of the ceramic surface, in the case of resolutions better than 200 μm (<; 100 μm) are subtle motifs practically impossible to print. To assure constant distance between ceramic surface and the dispensing unit is necessary to control Z axis level of the dispensing unit in conformity with corresponding actual value. This fact results from thixotropic materials physical behavior during the dispensing process, where distance fluctuation has to be smaller than 10 μm [1,2,3].

The new principle of dispensing system with the support of ultrasonic energy

This article describes the new possibility for higher quality deposition of thick film and similar materials with thixotropic character. Additional ultrasonic energy allows the local influence of the viscosity inside the dispensing system. Thixotropic character of materials in combination with selective effects of ultrasonic energy has a positive effect on the flow control and homogeneity inside the dispensing needle. The first results achieved by measurement of the system with ultrasonic energy describe the behavior of the dosing process. Measuring included the monitoring of the usual parameters of deposited layers as the width and thickness of lines, the possibility of creating radius and patterns with various shape. Additional energy does not change the basic methods of printed layers design, but allows move the resolution limits and ensure an optimal quality of leveling process already during the deposition. Optimization of dispensing head is tested in terms of benefits currently in possibility effect increases of resolution for printing technology of thick film materials for the production of hybrid integrated circuits. The optical comparison is selected as the evaluation for quality and dimensions of printed layers implemented in different trajectories of dispensing head movement.

Measurement of cooler efficiency

The article describes the construction of the wind box to evaluate the thermal conditions at the hardware parts of the computers. Aerodynamics box is accompanied by temperature sensors for monitoring temperature conditions at the inputs and outputs of the box. Measured element is specially designed heat source with homogenizer and temperature sensors. Motion measurement system is implemented to reduce the measurement errors in the analysis of thermal management system.

Comparing of simulation and experimental results of chip power interconnection

This paper describes recent developments made to the finite element modeling of wire bonding interconnection, extending its capability to handle viscoplastic behavior. In this project a test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards will be developed and realized. Especially the reliability of interconnections of semiconductor chips under high current regime until 10 A, or more, is emphasized.