Edita Hejatkova
Brno University of Technology
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Publication
Featured researches published by Edita Hejatkova.
Microelectronics International | 2004
J. Krejci; Jan Prasek; Lukas Fujcik; Sameh Khatib; Edita Hejatkova; Lubos Jakubka; Louisa Giannoudi
Screen‐printed electrodes are widely used in the construction of sensors. The use of graphite material is preferred due to its simple technological processing and low cost. Different graphite pastes are compared for hydrogen peroxide detection. The slope of the calibration curve, linearity and limit of detection have been compared for different pastes and technologies of graphite electrode preparation. The influence of the structure of the paste on response is discussed. Physical methods of sensitivity enhancement are proposed. All results are compared with platinum electrode as technological reference.
international spring seminar on electronics technology | 2010
Marek Novotny; Martin Bursik; Ivan Szendiuch; Edita Hejatkova; Jaroslav Jankovsky
This paper deals with the investigation of wire bonding power interconnection for standard CMOS chips, which is very important for power application. Base part of this research is the determination of power load by the wire. For testing are design two types of substrate, especially the FR4 and ceramic substrate. As a conductive thick film layer on the ceramic substrate is used two different pastes. First paste was AgPd and the second one AgPdPt. Various wire interconnections are made on each substrate. This contact are analyzing in term of power load. The evaluation of test is based on the value of power load, wire diameter, type of conductive layer on the substrate, etc.
electronics system integration technology conference | 2010
Martin Bursik; Edita Hejatkova; Jaroslav Jankovsky; Marek Novotny; Ivan Szendiuch
The reliable semiconductor chips wire bonding is one of the basic steps for the receiving good quality of final electronic system as well suitable economical solution. This paper describes some results obtained during our research work concerning development of the test equipment for high current stress measurement, for standard CMOS technology. High current density and high temperature gradient, which evoke in electronic devices the thermo mechanical stress, are the major reliability concerns for the future generation of high density power electronics. The developed Multi Channel High Current Test System is a PC based, stand alone driver and measurement tool, which is intended for the above described reliability testing. The equipment is able to measure small changes in connection resistance during long term reliability tests, where the contact is stressed by current up to 10 A. For this purpose was designed and realized in AMIS CMOS 0.7 technology semiconductor test chip (Fig. 1) that enable to measure maximum charge of current for different types of wires and served for study of chip pads degradation during increasing current load. The chip that includes heating resistor for simulation of temperature conditions was mounted on both, organic (FR-4) and inorganic (alumina) substrate to investigate chip pads degradation. Wire bonding was performed with different Al wire diameters (25µm, 50µm, 150µm and 300 µm, as well ribbon 150 × 13µm) and current capacity was investigated. Currently with this experimental work the modeling and simulation of electrical (current density and potential distribution) and thermo mechanical stressing were implemented. There was applied ANSYS to make the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. The first object was determining the stress distribution in connection wires because the most probably crack of the wire is in the place with the maximal stress value. Next object is the investigation of the current distribution in wires. The theoretical results are compared with test data of real experiment. The final aim of this paper is to show how to assure reliability of semiconductor chip for power interconnection and how to increase durability of these structures in the practical use. This paper describes some results achieved in the finite element modeling of wire bonding interconnection, extending its capability to handle visco-plastic behavior. A test system to be used in investigation and research on reliability of interconnections in integrated circuits and printed circuit boards is focused on investigation of interconnection reliability for semiconductor chips under high current regime until 10 A, or more.
electronics system integration technology conference | 2010
Ivan Szendiuch; Jaroslav Jankovsky; Martin Bursik; Edita Hejatkova
The lead-free soldering, required by RoHS legislative, has brought many new factors in the solder process as well in reliability and longevity of solder joints, which occur in high quantity in most electronic equipments and systems. In this paper is described a part of the research work, which runs at Brno University of Technology. The aim is to investigate some factors which influencing solder joint reliability and voids restriction, especially by reflow soldering process. The core factor for prediction and evaluation of solder joint reliability is solder joint structure that was monitored on scanning microscope for different solder compositions and processes, where some results were published last year [1]. Our experimental work has indicated that the solder joint structure is strong affected by temperature profile during reflow soldering, especially by speed of the cooling. That is why we have prepared special equipment for cooling to target this parameter for different types of solder materials. Obtained results have shown that the cooling phase has significant effect on solder joint structure formation, especially on creation and forming of intermetalic compounds. That means the cooling phase of the temperature reflow profile has to be setup very carefully to avoid problems with solder joint reliability. Further, we have been leaded new research work to influence the creating of solder joint structure by delivery of supplementary energy in reflow soldering process. First results have shown it could be other way, how to arrange and control better reflow process to assure higher reproducibility and quality of solder joints. Additionally we have tested patterns after thermal cycling by shear test. To make good comparison we studied together with SnPb alloy also SnAgCu (SnAg) and SnCuNiGe system.
international spring seminar on electronics technology | 2009
Martin Bursik; Edita Hejatkova; Michal Reznicek; Ivan Szendiuch; Cyril Vasko
This paper deals with presentation of some new aspects in study program of Microelectronics Technology on Faculty of Electrical Engineering and Communication Technology at Brno University of Technology. Microelectronics technology education makes a part of new study program that there was introduced in last years. This study program consists from three levels, Bachelor, Master and Doctorate degree. Subjects concerning Microelectronics technology make the fix part of this program and they are more and more popular among students from reasons concerning the practical education process. This fact is based on some new teaching activities that were incorporated in curriculum of both, bachelor and master subjects as shown in this paper.
global engineering education conference | 2012
Ivan Szendiuch; Martin Bursik; Michal Reznicek; Edita Hejatkova
This paper deals with the significant importance of the “Electronics Hardware” topic, which is introduced in the innovation program for Bachelor Study Program in the branch “Microelectronics and Technology” at Faculty of Electrical Engineering and Telecommunication (FEEC) in Brno University of Technology (BUT) in the Czech Republic. Importance of “Electronics hardware” knowledge is based upon the fact that mostly parts of engineers in all branches are in your praxis often in contact with electronics hardware. Electronics hardware ranges from individual chips to signal processing systems and instruments in various applications areas as communication and control equipments. These should be consumer, medical, automotive, informatics, telecommunication and many others. To manage hardware in the right way means to save cost, to assure quality and to care and protect about environment and human health. To help and create fundamentals in this way is the main contribution for the introducing this subject as interdisciplinary. The reason to involve this topic in the electric engineering education system is endorsed also by increasing interest of students from various branches for this topic in last three years of its introducing in education process. Detailed syllabus and lab exercises related to this topic are presented.
international spring seminar on electronics technology | 2011
Ivan Szendiuch; Martin Bursik; Edita Hejatkova
Article deals with the new approach to the education process focused on microelectronics technology and packaging that utilizes technology of Hybrid Integrated Circuits (HIC). It describes available methodology of teaching in terms of sequence of operations and possibilities for their adaptation to demonstrate basic principles from assembly and packaging of electronic circuits and systems in the experimental education.
international spring seminar on electronics technology | 2008
Petr Kosina; Edita Hejatkova; Josef Šandera
This paper is focused on the creation of bonding on a ceramic substrate medium, which can be applied in 3D structure (LTCC-low temperature co-fired ceramic), and on the measurement of its reliability. One of the methods which can be used to create a conductive connection between particular layers is described. The method enables to create complex circuitry and to increase the density of entities on the surface. The aim is to create the conductive connection of high reliability, because can not be nondestructive dissolution resultant structure.
international spring seminar on electronics technology | 2007
Edita Hejatkova; Marek Novotny; Ivan Szendiuch
The extent of wire bond ability of thick and thin film materials is determined by their mechanical properties. In the year 2006, there were introduced in EU new legislative regulations RoHS for materials used in electronics that have to exclude using of some chemicals, as for example Pb. This paper deals with verification of bondability and reliability of wire bonding ultrasonic process for lead-free thick film conductive materials. There were used some mechanical tests in the combination with temperature cycle aging. This testing was applied on two conductive thick film materials, one old and other lead free new.
european microelectronics and packaging conference | 2009
Ivan Szendiuch; Jiri Stary; Josef Šandera; Martin Bursik; Edita Hejatkova