Marina Tosi

Reliability study of phase-change nonvolatile memories

A detailed investigation of the reliability aspects in nonvolatile phase-change memories (PCM) is presented, covering the basic aspects related to high density array NVM, i.e., data retention, endurance, program and read disturbs. The data retention capabilities and the endurance characteristics of single PCM cells are analyzed, showing that data can be stored for 10 years at 110/spl deg/C and that a resistance difference of two order of magnitude between the cell states can be maintained for more than 10/sup 11/ programming cycles. The main mechanisms responsible for instabilities just before failure as well as for final device breakdown are also discussed. Finally, the impact of read and program disturbs are clearly assessed, showing with experimental data and simulated results that the crystallization induced during the cell read out and the thermal cross-talk due to adjacent bits programming do not affect the retention capabilities of the PCM cells.

4-Mb MOSFET-selected phase-change memory experimental chip

This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-/spl mu/m CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.

An 8Mb demonstrator for high-density 1.8V Phase-Change Memories

An 8Mb Non-Volatile Memory Demonstrator incorporating a novel 0.32 /spl mu/m/sup 2/ Phase-Change Memory (PCM) cell using a Bipolar Junction Transistor (BJT) as selector and integrated into a 3V 0.18 /spl mu/m CMOS technology is presented. Realistically large 4Mb tiles with a voltage regulation scheme that allows fast bitline precharge and sense are proposed. An innovative approach that minimizes the array leakage has been used to verify the feasibility of high-density PCM memories with improved Read/Write performance compared to Flash. Finally, cells distributions and first endurance measurements demonstrate the chip functionality and a good working window.

Data Retention Characterization of Phase-Change Memory Arrays

To support reliable large array products, phase-change memory (PCM) technologies must be able to retain data over the products lifetime with very low defect rates. PCM stores data in a chalcogenide material which can be placed in either a high resistance amorphous phase or a low resistance crystalline phase. Data retention is limited by resistance loss of the amorphous phase of the material, a process that is controlled by the kinetics of crystallization. This paper presents array-level data retention results on a statistical distribution of PCM cells that shows the failure rate with temperature to be well-described by the Arrhenius equation and distributed lognormally with time. For typical cells, the retention capability exceeds 100,000 hours at 85degC and is capable of meeting product requirements. In non-optimized devices, however, we observe cells that fail earlier than the lognormal distribution would predict. The failure distribution of these cells is Weibull with time but shows similar temperature acceleration to the intrinsic distribution, indicative of a defect in the amorphous chalcogenide. Characterization of these cells shows that their retention behavior is erratic. Furthermore, it is not significantly changed by write cycling. We then show that this defect distribution can be suppressed by process architecture or write algorithm optimization. Retention data collected on cells at both the 180nm and 90nm lithography nodes show that the intrinsic behavior is maintained with process scaling

4-Mb MOSFET-selected /spl mu/trench phase-change memory experimental chip

A /spl mu/trench Phase-Change Memory (PCM) cell with MOSFET selector and its integration in a 4-Mb experimental chip fabricated in 0.18-/spl mu/m CMOS technology are presented. A cascode bitline biasing scheme allows read and write voltages to be fed to the addressed storage elements with the required accuracy. The high-performance capabilities of PCM cells were experimentally investigated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to NOR Flash memories. Programmed cell current distributions on the 4-Mb array demonstrate an adequate working window and, together with first endurance measurements, assess the feasibility of PCMs in standard CMOS technology with few additional process modules.

Phase-change memory technology for embedded applications

A novel p-trench phase-change memory (PCM) cell and its integration with a MOSFET selector in a standard 0.18 /spl mu/m CMOS technology are presented. The high-performance capabilities of PCM cells are experimentally investigated and their application in embedded systems is discussed. Write times as low as 10 ns and 20 ns have been measured for the RESET and SET operation, respectively, still granting a 10/spl times/ read margin. The impact of the RESET pulse on PCH cell endurance has been also evaluated. Finally, cell distributions and first statistical endurance measurements on a 4 Mbit MOS demonstrator clearly assess the feasibility of the PCM technology.

Feasibility of steam tunnel oxide for advanced non volatile memories

Abstract In order to reduce dopant diffusion to obtain device scaling, a decrease of any thermal treatment is required. Therefore, to substitute dry thermal oxides for tunnel application in Flash Memories, the possibility of using steam oxides grown at low temperatures was studied, considering, in addition, scaling of these oxides for future generations. Results concerning oxide reliability and charge trapping for elementary structures are presented and correlated with device performance.