Tobias Koal

A software-based self-test and hardware reconfiguration solution for VLIW processors

Technology scaling inevitably leads to fabrication processes, which are more susceptible to production faults. At the same time, devices become more vulnerable to wear-out effects, which reduce the long term system reliability. The upcoming challenge of future designs is the development of integrated test and repair techniques dealing with both types of fault mechanisms. Our paper presents a built-in self-test (BIST) and repair solution for regular data path structures of VLIW processors by software-based self-test (SBST). After fault detection and localization by software a hardware reconfiguration, by using redundant components, takes place. Our software test and repair solution can be used to improve yield as well as reliability.

Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair

Reliability and the mean lifetime are major aspects in todays semiconductor device manufacturing. The continuous downscaling of transistor sizes and power supplies are the root causes of higher vulnerabilities of integrated circuits against time zero process variation, time dependent degradation and random faults induced by environmental influences like particle strikes. Handling permanent faults becomes inevitably a suitable solution to guarantee high reliabilities as well as increased lifetimes. Built-in self-repair is a possible solution, which exchanges faulty units with spare parts at the costs of extra hardware. In this paper, we evaluate the influence of different replacement strategies and their resulting additional hardware structures on reliability and mean lifetime. This analytical process allows to find the optimal replacement strategy for a given system, without implementing and synthesizing each case.

On the Feasibility of Built-In Self Repair for Logic Circuits

According to recent investigations on fault mechanisms in nano-scale integrated circuits, they suffer from wear-out effects that limit their life time seriously. For applications that combine a long life time and safety-critical functionality, means of fault compensation, de-stressing and eventual self repair are therefore becoming a must. This paper presents a circuit architecture that combines capabilities of self repair and de-stressing for logic circuits. Circuits that administrate repair functions are introduced. The necessary overhead for redundancy as well as for circuit re-organization is shown, depending on the granularity of repair. Finally limitations as well as single points of failure are discussed.

A Concept for Logic Self Repair

Predictions for the properties of integrated circuits and systems fabricated in emerging nano- technologies indicate a rising level of static and dynamic faults due to new fault mechanisms. Not only transient faults due to particle radiation are becoming a problem, but also wear-out effects on transistors and interconnects. While transient faults can be covered by well-known technologies such as error-correcting codes and triple modular redundancy, permanent faults essentially need a technology that provides built-in self repair (BISR). BISR is actually known and available for regular structures such as memory blocks, but is much more difficult to implement on irregular logic. The paper proposes a scheme for logic BISR, gives estimates for the associated overhead, and describes inherent limitations.

A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors

This paper presents a new in-the-field self-test approach for a specific VLIW processor model with emphasis on the diagnostic capability of the test. It is intended to be used as start-up test in-the-field in order to localize permanently defect components in a VLIW processor model, which provides self-repair capability. In order to overcome the drawbacks of several existing self-test techniques, a combination of them in a hierarchical manner is provided. By this, the data path of the VLIW processor can be checked within a very short time and at a fine grained diagnostic level. The results show that the required diagnostic resolution for the used processor model with self-repair capability can be obtained with a relatively small hardware overhead of about 6%.

Virtual TMR Schemes Combining Fault Tolerance and Self Repair

Nano-electronic circuits and systems with a minimum feature size of 45 nm and below exhibit an increasing variety of defect and fault mechanisms. Their rising sensitivity to radiation and coupling induced single and multiple event upsets is one problem, new or enhanced aging processes that lead to early lifetime failures (ELF) pose another threat. The compensation of transient fault effects is a well explored area of science, while repair technologies that tackle permanent faults have so far found a broad acceptance only for embedded memories and for FPGA-based systems. In this paper we describe two alternative schemes of fault detection and on-line error correction based on virtual and time-shared triple modular redundancy (TMR). Optionally, both schemes allow for optional built- in self repair at reasonable total cost.

Combining fault tolerance and self repair at minimum cost in power and hardware

Large-scale integrated circuits and systems fabricated in nano-technologies exhibit new and enhanced fault properties which limit both their reliability and their life time. Transient fault effects have found most attention so far. They must be handled by on-line check and fault compensation based on duplication and triplication, typically at a significant amount of extra power. Such techniques are not suitable for life time extension, since their redundant elements all undergo wear-out effects in hot operation. Repair technologies that perform a process of system re-organization and introduction of cold redundancy may extend system life time, but they are too slow to catch and correct transient and permanent fault effects in hot operation. The essential task therefore remains to find methods and architectures that will provide on-line check in combination with self repair techniques at a minimum cost in extra power.

An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC cores

The localization of permanent faults in a processor is a precondition for applying (self-)repair functions to that processor core. This paper presents a software-based self-test technique that can be used in the field for test and fault localization, there-by providing a high diagnostic resolution. It is shown how the self-test routine is adapted in the field to already detected faults in the processor, such that these faults do not affect the test- and diagnostic capability of the self-test routine. By this it becomes reasonable to localize multiple permanent faults in the processor. The proposed self-test is software-based, but it requires a few modifications of the processor. The feasibility of the technique is presented by an example; limitations are discussed, too.

Reconfigurable high performance architectures: How much are they ready for safety-critical applications?

Reconfigurable architectures are increasingly employed in a large range of embedded applications, mainly due to their ability to provide high performance and high flexibility, combined with the possibility to be tuned according to the specific task they address. Reconfigurable systems are today used in several application areas, and are also suitable for systems employed in safety-critical environments. The actual development trend in this area is focused on the usage of the reconfigurable features to improve the fault tolerance and the self-test and the self-repair capabilities of the considered systems. The state-of-the-art of the reconfigurable systems is today represented by Very Long Instruction Word (VLIW) processors and reconfigurable systems based on partially reconfigurable SRAM-based FPGAs. In this paper, we present an overview and accurate analysis of these two type of reconfigurable systems. The content of the paper is focused on analyzing design features, fail-safe and reconfigurable features oriented to self-adaptive mitigation and redundancy approaches applied during the design phase. Experimental results reporting a clear status of the test data and fault tolerance robustness are detailed and commented.

On the feasibility of combining on-line-test and self repair for logic circuits

Integrated circuits and systems implemented by using nano-technologies show a combination of known and new faults effects, which affect their reliability and their operational life time, specifically in safety-critical applications. Transient fault effects such as single and multiple event upsets (SEUs and MEUs) require fast error detection and compensation. Permanent faults may occur due to early life time failures on one side and stress-induced rapid aging on the other hand. They need to be compensated by repair technologies, preferably using “fresh” resources for the replacement of faulty functional units. As self repair is typically not a fast process and requires extra time while the system is off-line, on-line fault compensation must also catch and handle permanent faults that occur during “hot” operation. If on-line-test and error compensation on one side and repair technologies on the other hand are implemented independently, the resulting overhead in redundant circuitry becomes prohibitively high. In the following paper we therefore introduce a new concept of logic design which can meet the essential demands at reasonable cost using a flexible allocation of redundancy.