Marius E. Goosen

An 8×64 pixel dot matrix microdisplay in 0.35-μm complementary metal-oxide semiconductor technology

Microdisplay technologies for near-to-eye applications mostly use a complementary metal-oxide semiconductor (CMOS) processing chip as backplane for pixel addressing, with extensive post-processing on top of the CMOS chip to deposit organic LED or liquid crystal layers. Here, we examine the possibility of integrating emissive microdisplays within the CMOS chip, with absolutely no post processing needed. This will dramatically reduce the manufacturing cost of microdisplays and may lead to new microdisplay applications. Visible electroluminescence is achieved by biasing pn junctions into avalanche breakdown mode. The most appropriate CMOS pn junction is selected and innovative tech- niques are applied to increase the light extraction efficiency from the CMOS chip using the metal layers of the CMOS process. An 8 × 64 dot matrix microdisplay was designed and manufactured in a 0.35-μm CMOS technology. The experimental results show that a luminance level of 20 cd∕m 2 can be reached, which is an adequate luminance value in order to comfortably read data being displayed in relatively dark environ- ments. The electrical power dissipation per pixel being activated is 0.9 mW∕pixel. It is also shown that the pixels can be switched at a rate faster than 350 MHz.

High-speed CMOS optical communication using silicon light emitters

The idea of moving CMOS into the mainstream optical domain remains an attractive one. In this paper we discuss our recent advances towards a complete silicon optical communication solution. We prove that transmission of baseband data at multiples of megabits per second rates are possible using improved silicon light sources in a completely native standard CMOS process with no post processing. The CMOS die is aligned to a fiber end and the light sources are directly modulated. An optical signal is generated and transmitted to a silicon Avalanche Photodiode (APD) module, received and recovered. Signal detectability is proven through eye diagram measurements. The results show an improvement of more than tenfold over our previous results, also demonstrating the fastest optical communication from standard CMOS light sources. This paper presents an all silicon optical data link capable of 2 Mb/s at a bit error rate of 10-10, or alternatively 1 Mb/s at a bit error rate of 10-14. As the devices are not operating at their intrinsic switching speed limit, we believe that even higher transmission rates are possible with complete integration of all components in CMOS.

Integrated optical light directing structures in CMOS to improve light extraction efficiency

The directionality and external optical power of CMOS light sources was improved a factor 3.9 by implementing integrated light reflectors in an unmodified CMOS process. Implementing such reflectors successfully demonstrated a CMOS micro-display and a 350 MHz Si optical communication link.

Improved efficiency of CMOS light emitters in punch through with field oxide manipulation

Avalanche electroluminescence offers the opportunity for standard CMOS devices to be used as light emitters. Although inefficient, avalanche breakdown is inherently a fast process and potentially offers benefits in terms of speed when compared to emission based on forward biased junctions. Furthermore, the wide spectral characteristics of avalanche electroluminescence in the visible range also allows for some interesting applications. The main obstacle suppressing the use of these silicon light emitters in mainstream applications is inefficient radiative recombination. A number of techniques are known to improve quantum efficiency, one of which is operating the devices in punch through mode. This work focuses on improved results obtained from punch through devices, manipulation of the oxide above the radiative action and interesting results pertaining to the radiation pattern and the effects of LOCOS structures on the emission shape. This information could potentially benefit optical coupling to the light sources.

CMOS dot matrix microdisplay

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

A CMOS microdisplay with integrated controller utilizing improved silicon hot carrier luminescent light sources

Microdisplay technology, the miniaturization and integration of small displays for various applications, is predominantly based on OLED and LCoS technologies. Silicon light emission from hot carrier electroluminescence has been shown to emit light visibly perceptible without the aid of any additional intensification, although the electrical to optical conversion efficiency is not as high as the technologies mentioned above. For some applications, this drawback may be traded off against the major cost advantage and superior integration opportunities offered by CMOS microdisplays using integrated silicon light sources. This work introduces an improved version of our previously published microdisplay by making use of new efficiency enhanced CMOS light emitting structures and an increased display resolution. Silicon hot carrier luminescence is often created when reverse biased pn-junctions enter the breakdown regime where impact ionization results in carrier transport across the junction. Avalanche breakdown is typically unwanted in modern CMOS processes. Design rules and process design are generally tailored to prevent breakdown, while the voltages associated with breakdown are too high to directly interact with the rest of the CMOS standard library. This work shows that it is possible to lower the operating voltage of CMOS light sources without compromising the optical output power. This results in more efficient light sources with improved interaction with other standard library components. This work proves that it is possible to create a reasonably high resolution microdisplay while integrating the active matrix controller and drivers on the same integrated circuit die without additional modifications, in a standard CMOS process.

A high-speed 0.35μm CMOS optical communication link

The idea of integrating a light emitter and detector in the cost effective and mature technology which is CMOS remains an attractive one. Silicon light emitters, used in avalanche breakdown, are demonstrated to switch at frequencies above 1 GHz whilst still being electrically detected, a three-fold increase on previous reported results. Utilizing novel BEOLstack reflectors and increased array sizes have resulted in an increased power efficiency allowing multi-Mb/s data rates. In this paper we present an all-silicon optical communication link with data rates exceeding 10 Mb/s at a bit error rate of less than 10-12, representing a ten-fold increase over the previous fastest demonstrated silicon data link. Data rates exceeding 40 Mb/s are also presented and evaluated. The quality of the optical link is established using both eye diagram measurements as well as a digital communication system setup. The digital communication system setup comprises the generation of 232-1 random data, 8B/10B encoding and decoding, data recovery and the subsequent bit error counting.

A low switching time transmitter for high speed adaptive pre-emphasis serial links

Due to the advances in multimedia applications in recent years, the requirement for high user end bandwidth has increased significantly. The increase in data rates cause jitter requirements to become even more stringent. An adaptive finite impulse response (FIR) filter is proposed to compensate for the non-ideal channel causing data dependant jitter (DDJ), hence improving signal integrity. This paper proposes a current mode logic (CML) based transmitter which incorporates BiCMOS logic, to reduce the rise/fall times of the high speed transmitter. Simulation results of the BiCMOS CML transmitter is presented showing a 30 % improvement in rise/fall times under high current and high output load conditions.

Analysis of adaptive FIR filter pre-emphasis for high speed serial links

Due to the advances of technology in multimedia applications in recent years, the demand for high bandwidth point to point communication links has increased significantly. Jitter requirements have become more stringent with higher speed serial communication links. Jitter degrades the signal integrity at the receiver by introducing a timing deviation from the ideal or expected timing event. A proposal for reducing jitter, with the main focus on reducing data dependent jitter, is presented by employing adaptive finite impulse response (FIR) filter pre-emphasis. The channel bandwidth limitation, mainly caused by the skin effect of the conductor, and the parasitic components added by the integrated circuit package cause a nonflat frequency response and hence data dependent jitter. The pre-emphasis FIR filter is used to compensate for the frequency dependent chip package parasitic effects and the copper communication channel by altering the signal waveform before transmission. This paper presents the analysis and evaluation of adaptive FIR filter pre-emphasis to reduce data dependent jitter and to ultimately achieve higher data rates without adding significant implementation complexity. Simulation results on the adaptation scheme are also presented.

All-CMOS night vision viewer with integrated microdisplay

The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.