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Dive into the research topics where Jennifer A. Navarro is active.

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Featured researches published by Jennifer A. Navarro.


international symposium on microarchitecture | 1999

IBM's S/390 G5 microprocessor design

Timothy J. Slegel; Robert M. Averill; Mark A. Check; Bruce C. Giamei; Barry Watson Krumm; Christopher A. Krygowski; Wen H. Li; John Stephen Liptay; John Macdougall; Thomas J. McPherson; Jennifer A. Navarro; Eric M. Schwarz; Kevin Shum; Charles F. Webb

The IBM S/390 G5 microprocessor in IBMs newest CMOS mainframe system provides more than twice the performance of the previous generation, the G4. The G5 system offers improved reliability and availability, along with new architectural features such as support for IEEE floating-point arithmetic and a redesigned L2 cache and processor interconnect. The G5 system implements the ESA/390 instruction-set architecture, which is based on and compatible with the original S/360 architecture. Therefore, it has no RISC (reduced-instruction-set computing) concepts and is one of the most complex of all CISC (complex-instruction-set computing) architectures. Designers had to meet a unique set of challenges to achieve the G5s level of performance-for example, achieving a very high frequency given the complexity of the architecture.


Archive | 1998

System serialization with early release of individual processor

Charles F. Webb; Dean G. Bair; Mark S. Farrell; Barry Watson Krumm; Pak-Kin Mak; Jennifer A. Navarro; Timothy J. Slegel


Archive | 1998

Multiprocessor serialization with early release of processors

Charles F. Webb; Dean G. Bair; Mark S. Farrell; Barry Watson Krumm; Pak-Kin Mak; Jennifer A. Navarro; Timothy J. Slegel


Archive | 2008

SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR ENHANCING TIMELINESS OF CACHE PREFETCHING

Kattamuri Ekanadham; Jennifer A. Navarro; Il Park; Chung-Lung Kevin Shum


Archive | 2003

System and method for simultaneous access of the same line in cache storage

Mark A. Check; Jennifer A. Navarro; Chung-Lung K. Shum; Timothy J. Slegel; Aaron Tsai


Archive | 2012

SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER

Lisa C. Heller; Harald Boehm; Ute Gaertner; Jennifer A. Navarro; Timothy J. Slegel


Archive | 2003

Parallel cache interleave accesses with address-sliced directories

Jennifer A. Navarro; Chung-Lung K. Shum; Aaron Tsai


Archive | 2008

METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CROSS-INVALIDATION HANDLING IN A MULTI-LEVEL PRIVATE CACHE

Ka Shan Choy; Jennifer A. Navarro; Chung-Lung Kevin Shum; Aaron Tsai


Archive | 1995

Millicode extended memory addressing using operand access control register to control extended address concatenation

Mark S. Farrell; Barry Watson Krumm; Jennifer A. Navarro; Charles F. Webb


Archive | 2003

Re-fetch of long operand buffered remainder after cache line invalidation in out-of-order multiprocessor system without instruction re-execution

Mark A. Check; Jennifer A. Navarro; Chung-Lung K. Shum

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