Mark A. Ferriss

A 12.5 Mb/s to 2.7 Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback

A continuous-rate clock and data recovery (CDR) circuit that operates from 12.5 Mb/s to 2.7 Gb/s is described. The circuit automatically detects a change in input data rate, acquires the new frequency, and reports the data rate to the user without the need for an external reference clock or any programming. At 2.5Gb/s, it achieves an acquisition time of 1 ms. In tracking mode, it uses a dual DLL/PLL to provide superior jitter performance compared to a standard second-order loop. At the OC48 data rate, it achieves a jitter transfer bandwidth of 500 kHz and a jitter tolerance bandwidth of 3 MHz. It is on a 0.35-/spl mu/m double-poly, triple-metal (DPTM) BiCMOS process, dissipates 235 mA from a 3.3-V supply, and occupies 9 mm/sup 2/. It is in a compact 5/spl times/5 mm/sup 2/ LFCSP package.

A Linearized, Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing

This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of - 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is σ < 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 °C temperature variation is 3 dB. At the 25 GHz center frequency, the VCO FOMT is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

A fully-integrated dual-polarization 16-element W-band phased-array transceiver in SiGe BiCMOS

This paper presents a multi-function, dual-polarization phased array transceiver supporting both radar and communication applications at W-band. 32 receive elements and 16 transmit elements with dual outputs are integrated to support 16 dual polarized antennas in a package. The IC further includes two independent 16:1 combining networks, two receiver downconversion chains, an up-conversion chain, a 40GHz PLL, an 80GHz frequency doubler, extensive digital control circuitry, and on-chip IF/LO combining/distribution circuitry to enable scalability to arrays at the board level. The fully-integrated transceiver is fabricated in the IBM SiGe BiCMOS 0.13um process, occupies an area of 6.6×6.7mm2, and operates from 2.7V (analog/RF) and 1.5V (digital) supplies. Multiple operating modes are supported including the simultaneous reception of two polarizations with a 10GHz IF output, transmission in either polarization from an IF input, or single-polarization transmission/reception from/to I&Q base-band signals (2.5W RX, 2.9W TX). Measurement results show 8dB receiver NF and 2dBm transmitter output power per element at 94GHz in both polarizations.

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCOs small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of -126.5 dBc/Hz at 20.1 GHz and - 124.2 dBc/Hz at 24 GHz

A 28 GHz Hybrid PLL in 32 nm SOI CMOS

A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. In addition to the analog proportional path, the PLL includes a set of digital proportional path controls, so that the two approaches can be experimentally compared. At 28 GHz the RMS jitter is 199 fs (1 MHz to 1 GHz), phase noise is -110 dBc/Hz at 10 MHz offset. The 14 × 160 μm2 32 nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31 mA from a 1 V supply.

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

On-chip analog self-healing requires low-cost sensors to accurately measure various performance metrics. In this paper we propose a novel approach of indirect performance sensing based upon Bayesian model fusion (BMF) to facilitate inexpensive-yet-accurate on-chip performance measurement. A 25GHz differential Colpitts voltage-controlled oscillator (VCO) designed in a 32nm CMOS SOI process is used to validate the proposed indirect performance sensing and self-healing methodology. Our silicon measurement results demonstrate that the parametric yield of the VCO is improved from 0% to 69.17% for a wafer after the proposed self-healing is applied.

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits

The advent of the nanoscale integrated circuit (IC) technology makes high performance analog and RF circuits increasingly susceptible to large-scale process variations. On-chip self-healing has been proposed as a promising remedy to address the variability issue. The key idea of on-chip self-healing is to adaptively adjust a set of on-chip tuning knobs (e.g., bias voltage) in order to satisfy all performance specifications. One major challenge with on-chip self-healing is to efficiently implement on-chip sensors to accurately measure various analog and RF performance metrics. In this paper, we propose a novel indirect performance sensing technique to facilitate inexpensive-yet-accurate on-chip performance measurement. Towards this goal, several advanced statistical algorithms (i.e., sparse regression and Bayesian inference) are adopted from the statistics community. A 25 GHz differential Colpitts voltage-controlled oscillator (VCO) designed in a 32 nm CMOS SOI process is used to validate the proposed indirect performance sensing and self-healing methodology. Our silicon measurement results demonstrate that the parametric yield of the VCO is significantly improved for a wafer after the proposed self-healing is applied.

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels without loss of bandwidth. Transceiver circuit innovations are described including a low-skew transmission-line clock distribution, a 4:1 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SOI CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20” Megtron-6 PCB traces.

Indirect phase noise sensing for self-healing voltage controlled oscillators

The push for higher performance analog/RF circuits in scaled CMOS necessitates self-healing via post-manufacturing tuning. A major challenge with self-healing systems is the efficient design of on-chip sensors that capture the performance of interest. This is particularly difficult for metrics such as phase noise that are not easily measured on-chip. We propose an indirect sensing method that exploits the correlations between the performance metrics of interest and those that can be measured using easy-to-integrate sensors. We demonstrate indirect phase noise sensing for a 25GHz self-healing voltage controlled oscillator (VCO) design in 32nm CMOS SOI that approaches the best parametric yield achievable based on simulated results.

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.