Mark Beaverton Doczy

High performance fully-depleted tri-gate CMOS transistors

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

High-/spl kappa//metal-gate stack and its MOSFET characteristics

We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//metal-gate CMOS transistors with desirable threshold voltages.

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications

We demonstrate for the first time 85nm gate length enhancement and depletion mode InSb quantum well transistors with unity gain cutoff frequency, fT, of 305 GHz and 256 GHz, respectively, at 0.5V VDS, suitable for high speed, very low power logic applications. The InSb transistors demonstrate 50% higher unity gain cutoff frequency, fT, than silicon NMOS transistors while consuming 10 times less active power

High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack

We integrate a strained Si channel with HfO/sub 2/ dielectric and TiN metal gate electrode to demonstrate NMOS transistors with electron mobility better than the universal mobility curve for SiO/sub 2/, inversion equivalent oxide thickness of 1.4 nm (EOT=1 nm), and with three orders of magnitude reduction in gate leakage. To understand the physical mechanism that improves the inversion electron mobility at the HfO/sub 2//strained Si interface, we measure mobility at various temperatures and extract the various scattering components.

High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics

This paper reports, for the first time, the high-frequency response of NMOS and PMOS transistors in an integrated CMOS technology with 100 nm physical gate length and alternative gate dielectrics such as ZrO/sub 2/ and HfO/sub 2/ with TiN/PolySi gate electrode. It is shown that the dielectric constants of ZrO/sub 2/, HfO/sub 2/ and SiO/sub 2/ are invariant with respect to operating frequency at least up to 20 GHz. In addition, the cutoff frequency f/sub t/ of the 100 nm CMOS transistor test structures with ZrO/sub 2/ gate dielectric was measured to be equal to 46 GHz for NMOS and 47 GHz for PMOS. The corresponding f/sub t/ values for HfO/sub 2/ were 45 GHz for NMOS and 35 GHz for PMOS. High-K film transistors with 80 nm physical gate lengths, 7 /spl mu/m gate width and layout optimized for high frequency testing were also fabricated. The NMOS devices achieved an f/sub t/ of 83 GHz and an f/sub max/ of 35 GHz, while the PMOS yielded 41 GHz and 25 GHz respectively. These results are very similar to those of CMOS transistors with SiO/sub 2/ gate dielectric at similar physical gate lengths and widths. These results are very encouraging and suggest that high-K gate dielectrics can be used for high-frequency logic applications.