Simon Effler

Oversampled digital power controller with bumpless transition between sampling frequencies

In todays digitally controlled power supplies fast analog-digital converters sampling at a multiple of the switching frequency are used to reduce the latency time of the conversion. Conversely, in many cases the actual compensator is still sampled at the switching frequency which introduces an additional latency time. To reduce this latency time, a new compensator architecture is presented in this paper which allows a bumpless transition between two compensators operating at two different sampling frequencies. Operating at the switching frequency during steady-state provides noise suppression, while operating at the full “oversampling” frequency during transients reduces the compensators latency time significantly. A method for the bumpless transition between the two compensators is presented which is simple to implement and can be easily integrated into existing control architectures. Experimental verification demonstrates clear performance gain over existing control architectures.

Digital control law using a novel load current estimator principle for improved transient response

A method for the early detection of load transients using a current estimator for VR applications is presented. This technique combined with a new charge-balanced digital control law can improve the dynamic response to fast load transients. The key advantage of this new approach is the early detection of load transients which is independent of ADC sampling, where most existing solutions incorporate relatively expensive, complex and energy consuming high-speed ADCs. The presented method significantly reduces the inherent delay associated with fixed sampling detection in the control loop. The load current estimation during transient is critical for improved transient performance and allows the possibility of using a charge-balanced control law. Unlike existing algorithms, the presented control law is capable of implementing non-zero load lines required for VRMs. A full description of this control law is detailed. The current estimator technique and the charge-balanced digital control law are critically assessed using Matlab/Simulink. The resulting transient behaviour gives a significant improvement over conventional control schemes.

Efficiency-Based Current Distribution Scheme for Scalable Digital Power Converters

The trend in next-generation switched-mode power supplies will lead to modular, scalable solutions, which deliver power efficiently over a wide range of operation. This paper details a new approach to introduce more advanced control features to improve system efficiency into these scalable solutions. While these methods have been incorporated into multiphase converters in the past, they all require the distribution of information among the individual converters. An advantage of the proposed method is that it does not require such communication signals between the individual power supplies and is, therefore, fully scalable and cost effective. A system comprising individual, smart converters is proposed, where each converter regulates its respective output power to a level with high efficiency. Converters not required for the delivered output power are shut down. The proposed approach is analyzed theoretically. Implementation details for a field-programmable gate array experimental prototype system are given. The system performance for a four-converter prototype system is analyzed and discussed. The efficiency obtained is compared with the efficiency of a multiphase system with phase-shedding operation and the efficiency of a system with independent power converters without phase-shedding support.

Automated optimization of generalized model predictive control for DC-DC converters

Generalized predictive control (GPC) offers a method of designing digital compensators directly in the discrete-time domain. In this paper, an automatic design process based on the optimization of a few GPC parameters is presented. The application to DC-DC converters offers real benefits because of its clearly defined design process, time-domain performance criteria, simple tuning technique and guarantee of stability. For practical applications, the guarantee of stability may not be sufficient, certain performance criteria must also be achieved. In this design process, a performance index is used in the optimization routine to quantify specific performance objectives. A novel performance index is presented which weights performance and robustness for a more optimized compensator design. For illustration purposes an optimal GPC compensator is designed and tested for a buck converter. The resulting compensator is critically assessed in simulation and validated with experimental hardware.

Interrupt controller for DSP-based control of multi-rail DC-DC converters with non-integer switching frequency ratio

This paper proposes a hardware modification to a standard Digital Signal Processor (DSP) that enables it to digitally control multiple DC-DC converters with non-integer switching frequency ratios. The modified DSP overcomes the drawbacks of conventional DSPs, which are attributable to large variations in the delay from when the Analog to Digital Converter (ADC) samples the output voltage to when the duty cycle is updated. By incorporating modified interrupt control logic in the DSP, the effects of a variable delay are minimized by significantly reducing the worst case sampling to duty-cycle-updating delay. Applying this DSP to a multi-rail power supply system provides the designer with the flexibility to choose arbitrary switching frequencies for individual power converters, thereby allowing optimization of the efficiency and performance of the individual converters.

Oversampled digital controller IC based on successive load-change estimation for dc-dc converters

This paper presents an oversampled digital controller IC for low-power switch-mode power supplies (SMPS) that achieves fast response with a minimized addition of switching losses due to its control actions. To reduce the voltage deviation and improve converter response time, the controller samples the output voltage four times per switching cycle. A single voltage sample is processed by the conventional digital PID compensator to provide tight voltage regulation. Three additional samples are used to calculate the change in duty ratio value that results in the fastest possible response. If the load disturbance is significant, potentially causing large deviation, additional switching pulses are injected based on the estimated load change. To prevent operation at frequencies larger than the switching frequency, while still taking into account the results of oversampling, a novel oversampled digital pulse-width modulator (ODPWM) is introduced. The ODPWM adds or subtracts additional pulses such that the extra pulses are most effective in achieving fast recovery. The controller is implemented on-chip in CMOS 0.18µm technology. The complete controller occupies 0.53 mm2 of silicon area and takes only 5500 logic gates for the implementation. Its functionality and effectiveness are demonstrated on a 12-V-to−1.8-V, 60-W buck converter switching at 500 KHz. Compared to a fast PID compensator, having crossover frequency equal to 1/10th of the switching rate, the new IC reduces the voltage deviation by two times.

Automatic multi-phase digital pulse width modulator

Current demands on switched-mode power supplies to deliver higher output power with improved efficiency are leading to an increased use of multi-phase power converters. With an increasing number of phases, special multi-phase digital pulse width modulators (DPWMs) prove advantageous over the parallel use of conventional DPWMs. In this paper a “smart” multi-phase DPWM is presented which incorporates a duty cycle distribution algorithm. This algorithm is based on the fastest execution of the duty cycle input command with respect to the number of switching actions per phase and switching cycle. The system provides good dynamic current sharing during transients and enables the use of “faster” digital loop compensators. Intrinsic support of a variable number of active phases (phaseshedding operation) and improved scalability over conventional designs complete the feature set. The proposed system has been implemented on an FPGA system and tested with a four-phase buck converter.

Scalable Digital Power Controller With Phase Alignment and Frequency Synchronization

The trend in next-generation switched-mode power supplies will lead to modular, scalable solutions which deliver power efficiently over a wide range of operation. This paper details a new approach to introduce more advanced control features like phase-alignment and frequency synchronization into such scalable solutions. While these methods have been incorporated into multi-phase converters in the past, they all require the distribution of information among the individual converters. In distributed solutions, dedicated communication signals have been used to share this information. An advantage of the proposed method is that it does not require such communication signals between the individual power supplies and is therefore fully scalable and cost effective. Perturbances generated by the switching actions of the individual converters on the common input/output voltage are used by each converter to harvest information about the switching actions of its counterparts. An algorithm is proposed to align the individual phases and synchronize the switching frequencies based on this information. This allows a reduction of input/output capacitor ripple currents, similar to techniques used in multi-phase designs. Experimental results for an FPGA prototype implementation are presented.