Terry I. Chappell

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined. >

A room temperature 0.1 /spl mu/m CMOS on SOI

An advanced 0.1 /spl mu/m CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 /spl mu/m) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 /spl mu/m were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 /spl Aring/ effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C/sub L/=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained. >

Fast CMOS ECL receivers with 100-mV worst-case sensitivity

CMOS emitter-coupled logic (ECL) receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1- mu m technology. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differential mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying assumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process. >

A 0.18 /spl mu/m CMOS IA32 microprocessor with a 4 GHz integer execution unit

The processor has an execution unit with high bandwidth capability and low average instruction latency. The processor pipeline includes an Execution Trace Cache, Renamer, Scheduler, register file and execution unit. IA32 instructions are decoded when they are fetched from the L2 cache after a miss in the Execution Trace Cache. Serving as the primary instruction cache, the Execution Trace cache stores decoded instructions to remove the long delay for decoding IA32 instructions from this path, reducing the branch missprediction loop. Instruction traces follow the predicted execution path, not sequential instruction addresses. While this pipeline supplies the high bandwidth work stream, the length of this pipe contributes to instruction latency only when there is a branch miss-prediction (roughly once in 100 instructions).

The V-groove multijunction solar cell

A new type of silicon photovoltaic converter has been developed called the V-Groove Multijunction (VGMJ) solar cell. The VGMJ solar cell consists of an array of many individual diode elements connected in series to produce a high-voltage low-current output. All the elements of the cell are formed simultaneously from a single silicon wafer by V-groove etching. The results of detailed computer simulations predict a conversion efficiency in excess of 24 percent for this cell when it is operated in sunlight concentrated 100 or more times. The advantages of this cell over other silicon cells include the capability for greater than 20-percent conversion efficiency with only modest bulk carrier lifetimes, a higher open-circuit voltage, a very low series resistance, a simple one-mask fabrication procedure, and excellent environmental protection provided by a glass front surface.

SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time

In this paper a CMOS technology that is optimum for low voltage (in the I-volt range) applications is presented. Thin but undepleted SOI is used as the substrate, which gives low junction capacitance and no body effect. Furthermore floating body effects causes a reduction of subthreshold slope at high drain bias. This lowers the high-V/sub DS/ threshold to be used, which increases the current drive without significant increase in the off-current. This technology was applied to a high performance 512 Kb SRAM. Access time of 3.5 ns at 1 V was obtained.<<ETX>>

Self resetting logic register and incrementer

Register circuitry is described which is suitable for use with Self Resetting CMOS (SRCMOS) logic. It is level sensitive scan design (LSSD) compatible and complies with and implements the SRCMOS test modes. The register has been coupled to a novel high performance self resetting incrementer, which is based on a carry lookahead tree implemented in negative logic, and with a strobed final sum circuit. Hardware measurements are presented, showing a 900 ps 58-bit incrementer delay.

A study of the conversion efficiency limit of p + -i-n + silicon solar cells in concentrated sunlight

The conversion efficiency limit of p+-i-n+silicon solar cells in concentrated sunlight is explored with numerical simulations of an idealized p+-i-n+cell having field-induced junctions. Conversion efficiencies greater than 30 percent are calculated for this cell operating in sunlight concentrated 1000 times. The relative importance of bulk and surface recombination in limiting the cell conversion efficiency is illustrated for operation in 1 to 1000 suns. For surface recombination velocities below 100 cm/s, it is shown that bulk recombination losses limit the cell performance rather than recombination losses occurring in the p+or n+regions. The results show that Auger recombination in the bulk region will limit ultimately the cell conversion efficiency.

Determination of the oxygen precipitate-free zone width in silicon wafers from surface photovoltage measurements

Abstract A procedure has been developed for applying the surface photovoltage technique to the measurement of the width of the oxygen precipitate-free zone present at the surface of a thermally processed, Czochralski-grown silicon wafer. This procedure was developed through the use of a numerical simulation program which models the experimental determination of an effective diffusion lenght, L 0 , from surface photovoltage measurements on silicon wafers. The program predicts L 0 for a given precipitate-free zone diffusion length and thickness and bulk diffusion length. Results of the simulations show that for bulk diffusion lengths of 2 μ or less and a precipitate-free zone diffusion length greater than the thickness of the zone, W , the W ≡ 2.5 L 0 . Experimental results are presented which support the numerical findings.

On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM

On-chip test circuitry which provides 8-bit-deep ECL-level patterns to 12 input pads of a 512Kb CMOS ECL SRAM at cycle times as fast as 1.4 ns has been built in a 0.8¿m CMOS technology with Leff = 0.5¿m. A unique approach for synchronizing the input signals to the chip-select signal in order to provide optimum set-up time and data-valid window is described. Measured results and extensive simulation demonstrate the stability of the on-chip test circuitry for cycle times of 1.4 ns to 50 ns.