Mark W. Kuemerle

Memory Design Considerations for High-performance Networking SoCs

On chip memory in todays networking SoCs takes up >50% of total area and consumes >40% of total power. As demand for high-performance networks grows, so will the memory content on future SoCs. This paper presents IBMs 32nm HKMG SOI embedded memory offering discussing the considerations associated with the design of key networking memory functions. With memory limiting system performance and dictating minimum voltage system-level power and performance optimization are also presented.

An SOI technology optimized ASIC design system

Silicon on insulator (SOI) technology is an excellent choice for chip designs that require high performance and low power. IBMs SOI custom logic (ASIC) design system uses internal tools and flows in combination with solutions from a network of proven EDA vendors to support these high performance designs while managing the additional complexities introduced by the SOI process. The use of a qualified design system can add schedule predictability while simultaneously achieving high performance and power predictability. In this paper, we describe a high performance methodology for custom designs using a combination of Cadence, Synopsys, and IBM tools and flows. We discuss the benefits and challenges of the SOI technology and share results of high performance designs that were successfully manufactured using this methodology.