Marko Sokolich

Coherent singlet-triplet oscillations in a silicon-based double quantum dot

Silicon is more than the dominant material in the conventional microelectronics industry: it also has potential as a host material for emerging quantum information technologies. Standard fabrication techniques already allow the isolation of single electron spins in silicon transistor-like devices. Although this is also possible in other materials, silicon-based systems have the advantage of interacting more weakly with nuclear spins. Reducing such interactions is important for the control of spin quantum bits because nuclear fluctuations limit quantum phase coherence, as seen in recent experiments in GaAs-based quantum dots. Advances in reducing nuclear decoherence effects by means of complex control still result in coherence times much shorter than those seen in experiments on large ensembles of impurity-bound electrons in bulk silicon crystals. Here we report coherent control of electron spins in two coupled quantum dots in an undoped Si/SiGe heterostructure and show that this system has a nuclei-induced dephasing time of 360 nanoseconds, which is an increase by nearly two orders of magnitude over similar measurements in GaAs-based quantum dots. The degree of phase coherence observed, combined with fast, gated electrical initialization, read-out and control, should motivate future development of silicon-based quantum information processors.

Passive Millimeter-Wave Imaging Module With Preamplified Zero-Bias Detection

An analytical model and supporting measured data are presented for a preamplified W-band radiometer with a zero-bias detector appropriate for commercial millimeter-wave imaging cameras. Basic radiometer parameters, including RF bandwidth, are computed directly from simple low-frequency measurements and compare well with those obtained from RF measurements. A detailed analytical model shows how radiometer performance depends on internal component parameters, such as low-noise amplifier gain, noise factor, reflection coefficient, detector responsivity, etc. The measurements suggest that performance is sufficient for operation without a Dicke switch or mechanical chopping. A measured noise equivalent temperature difference of 0.45 K was obtained, assuming a single sensor is scanned across a focal plane, forming 32 pixels with 3.125-ms integration time per pixel. This sensitivity is considered sufficient by commercial manufacturers to obtain quality images in low-contrast (e.g., indoor) environments.

Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators

This paper examines the architecture, design, and test of continuous-time tunable intermediate-frequency (IF) fourth-order bandpass delta-sigma (BP /spl Delta//spl Sigma/) modulators. Bandpass modulators sampling at high IFs (/spl sim/100 MHz) allow direct sampling of the RF signal-reducing analog hardware and make it easier to realize completely software programmable receivers. This paper presents circuit design of and test results from continuous-time fourth-order BP /spl Delta//spl Sigma/ modulators fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 80 GHz and a maximum frequency of oscillation (f/sub MAX/) of about 130 GHz. Operating from /spl plusmn/5-V power supplies, a fabricated 180-MHz IF fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GS/s demonstrates stable behavior and achieves 75.8 dB of signal-to-(noise+distortion)-ratio (SNDR) over a 1-MHz bandwidth. Narrowband performance (/spl sim/1 MHz) performance of these modulators is limited by thermal/device noise while broadband performance (/spl sim/60 MHz), is limited by quantization noise. The high sampling frequency (4 GS/s) in this converter is dictated by broadband (60 MHz) performance requirements.

Pauli spin blockade in undoped Si/SiGe two-electron double quantum dots

We demonstrate double quantum dots fabricated in undoped Si/SiGe heterostructures relying on a double top-gated design. Charge sensing shows that we can reliably deplete these devices to zero charge occupancy. Measurements and simulations confirm that the energetics are determined by the gate-induced electrostatic potentials. Pauli spin blockade has been observed via transport through the double dot in the two electron configuration, a critical step in performing coherent spin manipulations in Si.

Measurement of valley splitting in high-symmetry Si/SiGe quantum dots

We have demonstrated few-electron quantum dots in Si/SiGe and InGaAs, with occupation number controllable from N = 0. These display a high degree of spatial symmetry and identifiable shell structure. Magnetospectroscopy measurements show that two Si-based devices possess a singlet N =2 ground state at low magnetic field and therefore the two-fold valley degeneracy is lifted. The valley splittings in these two devices were 120 and 270 {\mu}eV, suggesting the presence of atomically sharp interfaces in our heterostructures.

A low power 72.8 GHz static frequency divider implemented in AlInAs/InGaAs HBT IC technology

We report a 72.8 GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350 mV logic swing at less than 0 dBm input power up to a maximum clock rate of 63 GHz and requires 86 dBm of input power at the minimum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1 V power supply. To our knowledge this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is also the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1 V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power delay product for a static divider operating above 30 GHz in any technology.

Demonstration of sub-5 ps CML ring oscillator gate delay with reduced parasitic AlInAs/InGaAs HBT

We have demonstrated a gate delay of 4.9 ps and a power dissipation of 8 mW per CML inverter in an AlInAs-InGaAs HBT technology with 150 mV logic swing. The demonstration circuit was a 15-stage ring oscillator based on CML inverters with a fan-out of 1 and a nominal 3.1 V supply. The same circuit was measured to have a gate delay of 4.7 ps and a power dissipation of 13 mW per inverter using a 3.6 V supply, and a gate delay of 6.2 ps and a power dissipation of 2.4 mW per inverter with a 2.2 V supply. These are the fastest results for a bipolar transistor based logic family in any semiconductor and comparable to the fastest results for any logic family in any semiconductor. Because two gate delays are required for the simplest useful sequential logic circuits such as clocked flip-flops, this is a significant milestone in that it is the first, though somewhat idealized, demonstration that logic at 100 GHz is realizable in InP-based HBT.

Electric and Magnetic Tuning Between the Trivial and Topological Phases in InAs/GaSb Double Quantum Wells

Among the theoretically predicted two-dimensional topological insulators, InAs/GaSb double quantum wells (DQWs) have a unique double-layered structure with electron and hole gases separated in two layers, which enables tuning of the band alignment via electric and magnetic fields. However, the rich trivial-topological phase diagram has yet to be experimentally explored. We present an in situ and continuous tuning between the trivial and topological insulating phases in InAs/GaSb DQWs through electrical dual gating. Furthermore, we show that an in-plane magnetic field shifts the electron and hole bands relatively to each other in momentum space, functioning as a powerful tool to discriminate between the topologically distinct states.

Heterogeneous wafer-scale integration of 250nm, 300GHz InP DHBTs with a 130nm RF-CMOS technology

The performance advantages of InP based devices over silicon devices are well known, but the ability to fabricate complex, high transistor count ICs is limited both by the relative immaturity of the material system and a limited commercial market. Silicon based devices have made significant advances in device performance, but have not yet matched compound semiconductor device performance. A large commercial market, however, has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both of these technologies in order to enable a new class of high performance ICs. This work demonstrates the wafer scale integration of an advanced 250 nm, 300 GHz fT/fMAX InP DHBT technology with IBMs 130 nm RF-CMOS technology (CMRF8SF). Such integration allows the rapid adoption of more advanced CMOS and InP DHBT technology generations.

Edge Transport in the Trivial Phase of InAs/GaSb

We present transport and scanning SQUID measurements on InAs/GaSb double quantum wells, a system predicted to be a two-dimensional topological insulator. Top and back gates allow independent control of density and band offset, allowing tuning from the trivial to the topological regime. In the trivial regime, bulk conductivity is quenched but transport persists along the edges, superficially resembling the predicted helical edge-channels in the topological regime. We characterize edge conduction in the trivial regime in a wide variety of sample geometries and measurement configurations, as a function of temperature, magnetic field, and edge length. Despite similarities to studies claiming measurements of helical edge channels, our characterization points to a non-topological origin for these observations.