James Chingwei Li

Heterogeneous wafer-scale integration of 250nm, 300GHz InP DHBTs with a 130nm RF-CMOS technology

The performance advantages of InP based devices over silicon devices are well known, but the ability to fabricate complex, high transistor count ICs is limited both by the relative immaturity of the material system and a limited commercial market. Silicon based devices have made significant advances in device performance, but have not yet matched compound semiconductor device performance. A large commercial market, however, has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both of these technologies in order to enable a new class of high performance ICs. This work demonstrates the wafer scale integration of an advanced 250 nm, 300 GHz fT/fMAX InP DHBT technology with IBMs 130 nm RF-CMOS technology (CMRF8SF). Such integration allows the rapid adoption of more advanced CMOS and InP DHBT technology generations.

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.

Effects of device design on the thermal properties of InP-based HBTs

The authors study the effects of thermal resistance in InP-based HBTs with different vertical and lateral design. 3D simulations and measurement results illustrate that significant differences in thermal resistance can arise with relatively small changes in device structure. These results also highlight the significant thermal gradients within the transistor.

A submicrometer 252 GHz f/sub T/ and 283 GHz f/sub MAX/ InP DHBT with reduced C/sub BC/ using selectively implanted buried subcollector (SIBS)

The selectively implanted buried subcollector (SIBS) is a method to decouple the intrinsic and extrinsic C/sub BC/ of InP-based double-heterojunction bipolar transistors (DHBTs). Similar to the selectively implanted collector (SIC) used in Si-based bipolar junction transistors (BJTs) and HBTs, ion implantation is used to create a N+ region in the collector directly under the emitter. By moving the subcollector boundary closer to the BC junction, SIBS allows the intrinsic collector to be thin, reducing /spl tau//sub C/, while simultaneously allowing the extrinsic collector to be thick, reducing C/sub BC/. For a 0.35 /spl times/ 6 /spl mu/m/sup 2/ emitter InP-based DHBT with a SIBS, 6 fF total C/sub BC/ and >6 V BV/sub CBO/ were obtained with a 110-nm intrinsic collector thickness. A maximum f/sub T/ of 252 GHz and f/sub MAX/ of 283 GHz were obtained at a V/sub CE/ of 1.6 V and I/sub C/ of 7.52 mA. Despite ion implantation and materials regrowth during device fabrication, a base and collector current ideality factor of /spl sim/2.0 and /spl sim/1.4, respectively, at an I/sub C/ of 100 /spl mu/A, and a peak dc /spl beta/ of 36 were measured.

30.8 A 30GS/s double-switching track-and-hold amplifier with 19dBm IIP3 in an InP BiCMOS technology

High-speed track-and-hold amplifier (THA) circuits are critical for high-speed, high-resolution data converters, particularly in emerging 100Gb/s optical communication systems. High-speed CMOS analog-to-digital converters (ADCs) have been demonstrated to 56GS/s, but the linearity tends to rapidly degrade at high frequency. The use of a high-speed THA can broaden the frequency response, improve the distortion performance, and mitigate some of the timing requirements for high-speed time-interleaved ADCs. Recent THA work has leveraged high-fmax Indium Phosphide (InP) HBTs to implement 50GS/s track-and-hold amplifiers. Nonetheless, a two-chip solution consisting of an InP THA and time-interleaved CMOS ADCs is extremely difficult to package while retaining high-speed performance.

CMOS-integrated memristors for neuromorphic architectures

High-density memristor arrays are integrated on complementary metal-oxide-semiconductor (CMOS) substrates for neuromorphic circuit architectures. Advancing previously-reported work on Ag-filament memristor arrays [1], memristor operation is shown both in conjunction with CMOS multiplexer (MUX) circuits and in a “direct-access” configuration in which cross-bars are directly connected via CMOS interconnects to probe pads. The memristor arrays provide a high-density analog memory technology intended for CMOS-based neuromorphic architectures, Fig. 1 and [2]. Electrical data is shown for cross-bar arrays fabricated at 400-nm pitch with each memristor exhibiting intrinsic rectifying behavior, a beneficial feature for array operation. Forward-reverse-bias current ratios exceed 103 at ±1.5 V. Devices are programmed to four distinct resistance states, demonstrating utility as an analog memory with an effective number of bits (ENOB) of 2. Devices are fabricated and characterized across a 2” 180-nm-node CMOS wafer. Fabrication results are shown for 100-nm-pitch cross-bar arrays which enable effective bit densities greater than 1010 bits/cm2.

Experimental method to thermally deembed pads from R/sub TH/ measurements

Both compound semiconductor and silicon-based bipolar junction transistors or heterojunction bipolar transistors (HBTs) require the efficient removal of heat in order to achieve a maximum level of performance and reliability. In order to satisfy both of these criteria, the electrothermal behavior of each device must be captured in a compact model. The model parameter that determines the junction temperature is R TH, the thermal resistance. Experimental methods to determine RTH often require a relatively small device with a large R TH to be attached to a set of relatively large metal pads with a low RTH. The pads act as a thermal shunt to the substrate and artificially lower the measured RTH. In order to obtain a suitable RTH value for a device located in an IC, the pads must be deembedded from the measured data, much like pad deembedding for an S-parameter measurement. Test structures with various width metal traces between the emitter pad and devices emitter have been fabricated in a 200-GHz InP double HBT process. A method of using the measured RTH of these structures and a simple resistive network model to deembed the pads is presented. It is shown that deembedded values can be as much as 30% higher than the measured RTH

First demonstration of sub-0.25/spl mu/m-width emitter InP-DHBTs with > 400 GHz f/sub t/ and > 400 GHz f/sub max/

We report performance of sub-0.25/spl mu/m emitter-width InP/InGaAs/InP DHBTs. These are the smallest emitter-width III-V devices reported to date. Measured ft/fmax performance of 406GHz/423GHz is the first ever reported for a sub-0.25/spl mu/m emitter-width DHBT and among the fastest for any DHBTs. With the peak f/sub t/ and f/sub max/ performance occurring at I/sub c/ = 8mA (V/sub ce/ /spl sim/ 1.25V), this is the lowest power consumption DHBT ever reported with state of the art cutoff frequencies. The as-patterned emitter contact metal width for these devices was 0.25 /spl mu/m and the width of the emitter at the emitter-base junction is less than 0.25 /spl mu/m owing to undercutting of the underlying emitter semiconductor. When comparing with 0.4 /spl mu/m emitter width DHBTs, we find that 0.4 /spl mu/m device has the higher measured f/sub t/, /spl sim/ 420GHz, due to the lower emitter resistance for that emitter layout. F/sub max/ was highest for the 0.25/spl mu/m emitter devices due to lower base-collector mesa capacitance, C/sub bc/, which results from the reduced mesa width. We find this behavior to be consistent with scaling tradeoffs in the design of ultra-fast DHBTs.

A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process

A high-speed, track-and-hold amplifier and interleaved CMOS sample-and-hold circuit are implemented in an InP-on-CMOS fabrication process. Conventional 50- Ω interchip interconnects between III-V and CMOS circuits are eliminated with heterogeneous integration of III-V on CMOS, yielding higher performance circuits at lower power consumption. The track-and-hold amplifier is based on a double-switching feedback architecture using 250 nm InP HBTs and achieves an IIP3 of 19 dBm at a sampling rate of 30 GS/s. To the authors knowledge, this is the first published result of a high-speed track-and-hold amplifier in an InP BiCMOS process and the first implementation of a feedback linearized track-and-hold at a sampling rate above 2 GS/s. Additionally, a novel HBT buffer with feedback is demonstrated to offer high linearity and low power for driving time-interleaved CMOS sample-and-hold circuits. A 90 nm time-interleaved CMOS sample-and-hold circuit is demonstrated to achieve better than -53 dBc HD3 at a sampling rate of 5 GS/s while consuming roughly 24 mW per channel.

A wide-bandwidth W-band LNA in InP/Si BiCMOS technology

This paper presents the development of high-gain, wide-bandwidth, W-band LNA integrated circuits utilizing a novel 0.25 μm InP/Si BiCMOS process with Ft/Fmax of 330/270 GHz. A 4-stage microstrip LNA achieves a minimum NF of 5.7 dB at 92 GHz and remains less than 7.2 dB (6.4 dB avg.) across a 75-100 GHz bandwidth. The LNA also exhibits a peak gain of 27.7 dB, a 3-dB bandwidth of 18 GHz (80-98 GHz), gain > 20 dB over 75-110 GHz, while consuming only 19.2 mW of DC power from a 1.2V supply. Additionally, individual bias control for each device has been incorporated to vary gain, including a version with two 3-bit current steering DACs to control base currents. The 0.42 mm2 (w/o pads) LNA is suitable for many emerging W-band applications including radar, communications, and imaging and provides superior performance compared to published LNAs developed in available SiGe BiCMOS technologies.