Ali Fazli Yeknami

Low-Power DT

A comparative design study of ultra-low-power discrete-time ΔΣ modulators (DT ΔΣMs) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive filter. Two design variants of 2nd-order ΔΣMs are analyzed and compared to a power-optimized standard active modulator (ΔΣM_AA). The first variant (ΔΣM_AP) employs an active filter in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣM_PP) makes use of passive filters in both stages. For practical verification, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣM_AA, ΔΣM_AP, and ΔΣM_PP achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣM_PP can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.

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A 0.7 V 400 nW fourth-order active-passive ΔΣ modulator with one active stage is presented in this paper using standard CMOS 65 nm technology. The modulator achieves 84 dB SNR and 80.3 dB SNDR in a signal bandwidth of 500 Hz with a sampling frequency of 256 kHz. The input-feedforward architecture is used to improve the voltage swing before the comparator of the traditional passive modulators, which enables simpler comparator design with no preamplifier as well as cascading three successive power-efficient passive filters. The first active stage is used to reduce the comparators noise and offset and to minimize the capacitive area. The modulator achieves a high power-efficiency (47 fJ/step) in terms of widely used figure of merit.

Modulators Using SC Passive Filters in 65 nm CMOS

A new passive switched-capacitor low-pass filter topology is presented. The sampling rate is high due to the reduced number of clock phases and switches connected to each capacitor. Also, this scheme decreases the filter nonlinearity. Verified by simulations, the noise analysis of the filter shows superior performance compared to active SC filters. These features, and a wide frequency tuning range, make the filter suitable for high-speed, low noise, and low power applications. A 7th-order 400 MS/s filter was designed in 0.18 μm AKM CMOS technology. Simulations verify that it can achieve over 100 dB attenuation at 200 MHz frequency, while consuming only dynamic power.

A 0.7-V 400-nW fourth-order active-passive ΔΣ modulator with one active stage

A 0.5-V ultra-low-power second-order DT ΔΣ modulator is presented in this paper for medical implant devices. The modulator employs 2nd-order passive low-pass filter and ultra-low-voltage building blocks, including preamplifier, regenerative comparator, and clock controller, in order to enable operation near 0.5 V supply. A low-noise and gain-enhanced single-stage preamplifier is developed using a body-driven technique. Passive filter is gain boosted by power-efficient charge-redistribution amplification scheme. Designed in a 65nm CMOS technology, the modulator achieves 65 dB peak SNDR over a 500 Hz signal bandwidth, while it consumes 250 nW from a 0.5 V supply. The modulator is functional at 0.45V and obtains 52 dB SNR, while consuming 200 nW.

A passive CMOS low-pass filter for high speed and high SNDR applications

In this paper, a new asymmetric 6T (AS6T) SRAM cell is presented in a standard 90-nm CMOS technology employing separate bitline and wordline for read operation. Utilizing separate bitline and wordline during read operation decouples the other cell node from the bitline, hence, enhancing the read static noise margin (SNM) by almost 2 times as compared to the conventional 6T SRAM. The read SNM of 6T and AS6T SRAM cells during a read operation in 1.0 V supply is 85 mV and 159 mV, respectively. The mean μ of the hold SNM for both cells are well above 140 mV, however, the μ of the conventional 6T SRAM is larger than that of AS6T cell. The impact of process parameter variations on read and hold noise margin of the asymmetric 6T cell and the conventional 6T cell, considering various supply voltages, is investigated. The results demonstrate yield improvement, up to 99.5%, and indicate that the supply voltage can scale down to 0.45 V.

A 0.5-V 250-nW 65-dB SNDR passive ΔΣ modulator for medical implant devices

This paper presents the design and implementation of a variable bandwidth amplifier intended for ultra-low-power biomedical implants in 65nm CMOS, providing tunable gain-bandwidth in three modes: 0.9 MHz, 1.7 MHz, and 2.3 MHz with consistent 56 dB DC gain. The amplifier consumes 180nW static power in the lowest bandwidth mode, and consumes 315 nW static power in the full bandwidth mode with an 8 pF load from a 0.9-V supply voltage. To illustrate the concept, the presented programmable bandwidth amplifier is applied in a dual-mode ΔΣ modulator aiming for sensing/measuring stage of a cardiac pacemaker.

A low voltage and process variation tolerant SRAM cell in 90-nm CMOS

A low-voltage low-power fourth-order active-passive ΔΣ modulator with one active stage is presented. The input-feedforward architecture is adopted, which improves the voltage swing prior to the quantizer. This enables a simpler comparator design and cascade of three passive filters. The passive integrator, as an alternate option to its power-hungry active counterpart, and the non-idealities associated with it are investigated. The active integrator used at the input stage provides most of the loop gain, which suppresses the thermal noise from the succeeding stages and minimizes the non-idealities in the comparator, such as noise and offset. The active integrator employs a two-stage amplifier with load compensation, whose DC-gain is boosted by a partially body-driven technique. The modulator, operated from a 0.7 V supply and clocked with 256 kHz sampling frequency, achieves 84 dB SNR and 80.3 dB SNDR over a 500 Hz signal bandwidth, while it dissipates only 400 nW power.

A variable bandwidth amplifier for a dual-mode low-power ΔΣ modulator in cardiac pacemaker system

This paper presents a low-power 2nd-order discrete-time (DT) ΔΣ analog-to-digital converter (ADC) aimed for medical implant devices. The designed ΔΣ modulator with two active integrators (filters) employs power-efficient two-stage load-compensated OTAs with minimal load and rail-to-rail output swing, which provides higher power-efficiency than the two-stage Miller OTA. The modulator, implemented in a 65nm CMOS technology with a core area of 0.033 mm2, achieves 76-dB peak SNDR over a 500 Hz signal bandwidth, while consuming 2.1 μW from a 0.9 V supply voltage. Compared to previously reported modulators for such signal bandwidths, the achieved performance (FOM of 0.4 pJ/step) make the presented modulator one of the best among sub-1-V modulators in term of most commonly used figure of merit.

Low-Power Low-Voltage ΔΣ Modulator Using Switched-Capacitor Passive Filters

This paper presents a novel approach to design a programmable-bandwidth amplifier intended for ultra-low-power switched-capacitor application. The proposed topology is based on the common load-compensated two-stage OTA. The GBW is enhanced by replicating the second amplifying stage. Implemented in a 65-nm CMOS technology and approved by the post-layout simulation, the GBW is programmed in three operation modes (400, 700, and 900 kHz), while 52-dB DC gain is preserved in a 5-pF load. The OTA consumes 275-nW static power in a 400 kHz unity-gain frequency and 375-nW static power in a 900 kHz unity-gain frequency from 0.9-V supply.