Christian Tobias Banzhaf

Characterization of Diverse Gate Oxides on 4H-SiC 3D Trench-MOS Structures

This study focuses on the characterization of silicon dioxide (SiO2) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (DIT) of 1*1011 cm-2 eV-1 under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.

Trench-MOSFETs on 4H-SiC

This paper introduces n-channel normally-off Trench-MOSFETs on 4H-SiC featuring a blocking voltage of 600 V and 1200 V. The Trench-MOSFETs exhibit a specific room temperature on-state resistance RDS,on of 1.5 mΩ cm² and 2.7 mΩ cm², respectively. It is shown that a further reduction of the RDS,on by approximately 25 % can be achieved using square-shaped or hexagonal unit cells instead of stripe-shaped unit cells. The Trench-MOSFET switching characteristics using a double pulse setup with a switching current Isw of 100 A and a switching voltage Vsw of 450 V is presented and discussed. The short turn-off and turn-on times in the range of several ten nanoseconds yield large maximum disw/dt and dvsw/dt values, which enable highly efficient power conversion with low switching losses.

Impact of Post-Trench Processing on the Electrical Characteristics of 4H-SiC Trench-MOS Structures with Thick Top and Bottom Oxides

This study focuses on the evaluation of different post-trench processes (PTPs) for Trench-MOSFETs. Thereto, two different types of inert gas anneals at process temperatures above 1250 °C are compared to a sacrificial oxidation as PTP. The fabricated 4H-SiC Trench-MOS structures feature a thick silicon dioxide (SiO2) both at the wafer surface (‘top’) and in the bottom of the trenches (‘bottom’) in order to characterize only the thin gate oxide at the trenched sidewalls. It is shown that an inert gas anneal at a process temperature between 1400 °C and 1550 °C yields uniform current/electric field strength (IE) values and excellent dielectric breakdown field strengths up to 12 MV/cm using a SiO2 gate oxide of approximately 40 nm thickness. Charge-to-breakdown (QBD) measurements at a temperature T of 200 °C confirm the necessity of a high temperature inert gas anneal after 4H-SiC trench etching in order to fabricate reliable Trench-MOS devices. QBD values up to 16.2 C/cm² have been measured at trenched and high temperature annealed sidewalls, which is about twice the measured maximum QBD value of the corresponding planar reference MOS structure. The capacitive MOS interface characterization points out the need for a sacrificial oxidation subsequent to a high temperature inert gas anneal in order to ensure a high quality MOS interface with excellent electrical properties.

Investigation of Trenched and High Temperature Annealed 4H-SiC

This study focuses on the effects of a high temperature anneal after dry etching of trenches (post-trench anneal, PTA) on 4Hsilicon carbide (4H-SiC). We aim at the optimum 4H-SiC post-trench treatment with respect to the fabrication and the operation of a trenched gate metal oxide semiconductor field effect transistor (Trench-MOSFET). PTA significantly reduces micro-trenches, also called sub-trenches [, in the corners of the bottom of the trench. This is highly beneficial in case the etched trench sidewall is used as the channel of a Trench-MOSFET. However, PTA is also shown to cause a slight enlargement of the trench width along with a considerable increase of the substrate surface roughness. In addition, X-ray photoelectron spectroscopy (XPS) depth profiles indicate an increased carbon atom concentration at the 4H-SiC surface after the high temperature PTA. The non-stoichiometric surface composition affects the quasi-static capacitance-voltage (QSCV) behavior of MOS structures using a deposited gate oxide (GOX). We assume that a sacrificial oxidation directly after the PTA could restore a stoichiometric 4H-SiC surface.

Influence of Diverse Post-Trench Processes on the Electrical Performance of 4H-SiC MOS Structures

This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.